24X32BL Search Results

Contextual Info: 24x32BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and

Contextual Info: 24x32BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - V iaLink" metal-to-metal program m able-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and

PF144

Abstract: PQ208
Contextual Info: 24x32BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and

8000l

Abstract: PF144 PQ208
Contextual Info: 24x32BL Wild Cat 8000L Low Power 3.3 Volt Operation, 8K Gate FPGA 2 High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and

Contextual Info: 24X32BL WildCaX 8000L Low Power 3.3 Volt Operation, 8K Gate FPGA P 5V Tolerant I/Os - Support interface to 5 V o lt C M O S , N M O S and bipolar devices by sinking up to 12 m A see IIH specification . .8000 usable gates, 180 I/O pins Q| High Usable Density - A 24-by-32 array o f768 logic cells provides 24,000