24JUN2005 Search Results

Contextual Info: SN74LVC541A-Q1 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS713A – SEPTEMBER 2003 – REVISED JUNE 2005 FEATURES • • • • • • • • • • • 1 DW OR PW PACKAGE (TOP VIEW) Qualification in Accordance With AEC-Q100 (1) Qualified for Automotive Applications

Contextual Info: TFP501 PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI) and High-Bandwidth Digital Content Protection

Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A − DECEMBER 2000 − REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1

Contextual Info: SN74LVC1G32-EP SINGLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES458A – DECEMBER 2003 – REVISED NOVEMBER 2005 FEATURES • • • • • • • 1 • • • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: DGN-8 D-8 THS4502-EP THS4503-EP www.ti.com SGLS291 − APRIL 2005 WIDEBAND, LOWĆDISTORTION FULLY DIFFERENTIAL AMPLIFIERS FEATURES D Controlled Baseline D One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of −555C D D D D D

Contextual Info: SN74ACT08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCAS779 − SEPTEMBER 2004 D Controlled Baseline D D D D D Inputs Accept Voltages to 5.5 V D Max tpd of 10 ns at 5 V D Inputs Are TTL-Voltage Compatible − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: SN74HC21ĆQ1 DUAL 4ĆINPUT POSITIVEĆAND GATE SCLS597 − NOVEMBER 2004 D Qualification in Accordance With D D D D D D D D D OR PW PACKAGE TOP VIEW AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With

Contextual Info: TFP501 PanelBus HDCP DIGITAL RECEIVER SLDS127B − JULY 2001 − REVISED AUGUST 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI) and High-Bandwidth Digital Content Protection

Contextual Info: SN74HCT04ĆEP HEX INVERTER SCLS561 − JANUARY 2004 D Controlled Baseline D D D D D − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification Qualification Pedigree† Operating Voltage Range of 4.5 V to 5.5 V

74AC11648

Contextual Info: 74AC11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS114 – MARCH 1990 – REVISED APRIL 1993 • • • • • • • • DW OR NT PACKAGE TOP VIEW Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths

Theta-JC

Contextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120B - MARCH 2000 − REVISED JUNE 2003 D Supports UXGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1

Contextual Info: SN74ALS819, SN74ALS29818 8-BIT DIAGNOSTICS/PIPELINE REGISTERS SDAS105A – JANUARY 1986 – REVISED OCTOBER 1986 • • • • description The SN74ALS819 and SN74ALS29818 are 8-bit pipeline registers each with an on-chip shadow register. They are for use in applications such as

Contextual Info: SN54ABT16374, SN74ABT16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS454 - APRIL 1991 - REVISED JULY 1993 • • • • • • • • • SN54ABT16374 . . . WD PACKAGE SN74ABT16374 . . . DL PACKAGE TOP VIEW Members of the Texas Instruments

74AC11013

Contextual Info: 74AC11013 DUAL 4-INPUT POSITIVE-NAND SCHMITT TRIGGER SCAS112 – MARCH 1990 – REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity Flow-Through Architecture Optimizes PCB

Contextual Info: 74AC11378 HEX D–TYPE FLIP–FLOP WITH CLOCK ENABLE SCAS150 – APRIL 1991 – REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE Contains Six D-Type Flip-Flops Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage

SN751518

Contextual Info: SN751508, SN751518 DC PLASMA DISPLAY DRIVERS SLDS035 − JANUARY 1987 − REVISED NOVEMBER 1989 D Each Device Drives 32 Lines D −120-V PNP Open-Collector Parallel D D D D SN751508 . . . FT PACKAGE TOP VIEW Outputs High-Speed Serially Shifted Data Inputs

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: 74AC11160 SYNCHRONOUS 4ĆBIT DECADE COUNTER ą ą SCAS380 − D3199, AUGUST 1988 − REVISED APRIL 1993 • • • • • • • • Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Fully Synchronous Operation for Counting Flow-Through Architecture to Optimize PCB

74AC11533

Contextual Info: 54AC11533, 74AC11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS ą SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • • • 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE 8-Latches in a Single Package

Contextual Info: 74AC11194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER SCAS093 − NOVEMBER 1989 − REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE Parallel-to-Serial, Serial-to-Parallel Conversions Left or Right Shifts Parallel Synchronous Loading

Contextual Info: 74AC11153 DUAL 1ĆOFĆ4 DATA SELECTOR/MULTIPLEXER ą ăą SCAS117A − JUNE 1990 − REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE TOP VIEW Permits Multiplexing From N Lines to 1 Line Performs Parallel-to-Serial Conversion Strobe (Enable) Line Provided for

Contextual Info: 74AC11378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS150 − APRIL 1991 − REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE Contains Six D-Type Flip-Flops Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage

74ACT11657

Contextual Info: ą 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3ĆSTATE OUTPUTS SCAS232 − AUGUST 1992 − REVISED APRIL 1993 • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout

Contextual Info: 74AC11593 8ĆBIT BINARY COUNTER WITH 3ĆSTATE I/O INPUT REGISTERS ą SCAS202 − MARCH 1992 − REVISED APRIL 1993 • • • • • • • DW OR NT PACKAGE TOP VIEW Parallel 3-State I/O: Register Inputs/ Counter Outputs Counter Has Direct Overriding Load and