2117 RAM Search Results

ly2117

Abstract: LY 2117 20/LY 2117 intel 2117 S1123 40ns-e S6054 s6055
Contextual Info: inteT 2117 FAMILY 16,384 x 1 BIT DYNAMIC RAM 2117-2 2117-3 2117-4 Maximum Access Time ns 150 200 250 Read, Write Cycle (ns) 320 375 410 Read-Modify-Write Cycle (ns) 330 375 475 Non-Latched Output is Three-State, TTL Compatible RAS Only Refresh 128 Refresh Cycles

application IR 2117

Abstract: compensator 2N3904 MBR0530T1 2116a
Contextual Info: NX2116/2116A/2116B/2117/2117A SYNCHRONOUS PWM CONTROLLER WITH CURRENT LIMIT, POWER GOOD & OVER VOLTAGE PRELIMINARY DATA SHEET Pb Free Product FEATURES DESCRIPTION The NX2116/2117 family of products are synchronous n Bus voltage operation from 2V to 25V Buck controller IC designed for step down DC to DC n Power Good indicator available in NX2116

Contextual Info: NX2116/2116A/2116B/2117/2117A SYNCHRONOUS PWM CONTROLLER WITH CURRENT LIMIT, POWER GOOD & OVER VOLTAGE PRELIMINARY DATA SHEET Pb Free Product FEATURES DESCRIPTION The NX2116/2117 family of products are synchronous n Bus voltage operation from 2V to 25V Buck controller IC designed for step down DC to DC n Power Good indicator available in NX2116

8202a intel microprocessor pin diagram

Abstract: 2118 intel dynamic ram system of 8088 microprocessor 2118 dynamic ram 8202A multibus of intel 8085 CA1270 ah41 Intel 2118 2118 ram
Contextual Info: in t e i 8202A DYNAMIC RAM CONTROLLER • Provides Transparent Refresh Capability Provides All Signals Necessary to Control 2104A, 2117, or 2118 Dynamic Memories Directly Addresses and Drives Up to 128K Bytes Without External Drivers ■ Fully Compatible with Intel 8080A,

intel 8202

Abstract: S202A 8202a intel microprocessor pin diagram intel 8202 DYNAMIC CONTROLLER intel 8088 memory 4511 pin configuration 8202A 8202 rq block diagram pin diagram of ic 4511 TCA 4511
Contextual Info: intéf 8202A DYNAMIC RAM CONTROLLER Provides All Signals Necessary to Con­ trol 2117, or 2118 Dynamic Memories • Provides Transparent Refresh Capability Directly Addresses and Drives Up to 64K Bytes Without External Drivers ■ Fully C o m p atib le w ith Intel 8 0 8 0 A ,

memory ic 2118

Abstract: 8202A Dynamic RAM Controller 8202a intel microprocessor pin diagram
Contextual Info: inteT 8202A DYNAMIC RAM CONTROLLER • Provides All Signals Necessary to Con­ trol 2117, or 2118 Dynamic Memories ■ Provides Transparent Refresh Capability ■ Directly Addresses and Drives Up to 64K Bytes Without External Drivers ■ Fully C o m p atib le w ith Intel 8 0 8 0 A ,

Nidec motor

Contextual Info: COPAL ELECTRONICS HALOGEN FREE LEAD FREE DP7115 32-Tap Digital Potentiometers DP FEATURES APPLICATIONS • 32-position, linear-taper potentiom eter Autom ated product calibration • Low power CMOS technology Rem ote control adjustm ents • Single supply operation: 2.5V-5.5V

ferrite eddy current hysteresis loss

Abstract: eddy current hysteresis loss core eddy current hysteresis loss Summit Microelectronics
Contextual Info: Application Note 60 Achieving High Efficiency in a High-current Integrated Buck Switching Regulator Shadi Hawawini Introduction Many of today’s modern mobile electronics require more power and higher current than ever before. Mobile electronics are becoming increasingly feature rich, and

Contextual Info: Section 21 Electrical Specifications 21.1 Absolute Maximum Ratings Table 21-1 lists the absolute maximum ratings. Table 21-1 Absolute M aximum Ratings Item Symbol Rating Unit Supply voltage v cc -0 .3 to + 7.0 V Programming voltage Vpp -0 .3 t o +14.0 V Input voltage at ports not

A-18

Abstract: MPC555 QADC64 272-Pin
Contextual Info: LIST OF TABLES Table 2-1 2-2 2-3 2-4 2-5 2-6 Title Page MPC555 Pin Functions for 272-Pin PBGA . 2-3 Pin Functionality Table . 2-6

ma 1050

Contextual Info: jyfaœm Low Noise Amplifier, 28 dB Gain 100-600 MHz • 1.6 Typical Midband Noise Figure ■ + 19 dBm Typical 1 dB Compression Point ■ + 30 dBm Typical Third Order Intercept Point AM-160 .18 3.7 0±100.0 _1 2 .41 S * _0900*0.005 (22.86±0.13)H FP-9 0500

AmPAL18

Abstract: AMPAL18P8B/AL/A/L
Contextual Info: COM’L H AmPAL.18P8B/AL/A/L Advanced Micro Devices 20>Pin Combinatorial TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 15 ns maximum propagation delay ■ Universal combinatorial architecture ■ Prog rammable output polarity ■

3004x

Abstract: SIEMENS B 58 451 GE 639 transistor 2114D transistor bfx 73 STATIC RAM 2114 Q2114 tic 2116 M
Contextual Info: ESC D fl23SbOS 0G04737 fl ¡SIEG r - j/ 'Z 3 B FX 55 NPN Silicon Transistor for VHF Output Stages in Broadband Amplifiers SIEMENS A K T IE NÖES EL LS CH AF BFX 55 is an epitaxial NPN silicon planar transistor in a TO 39 case 5 C 3 DIN 41873 . The collector has been electrically connected to the case. The transistor is especially suitable for

1502B

Abstract: cmos dynamic ram 256kx1 p4c1257
Contextual Info: PERFORMANCE SEMICONDUCT OR 20E D TObBST? DQD0t,33 T P4C1257/P4C1257L ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS SCRAMS FEATURES • High Speed (Equal Access and Cycle Times) - 20/25/30/35 ns (Commercial) - 25/30/35/45/55 ns (Military) Data Retention with 2.0V Supply

C004

Abstract: MPC555 QADC64 417F
Contextual Info: APPENDIX A MPC555 INTERNAL MEMORY MAP The tables below use the following notations. In the Access column: S = Supervisor Access Only U = User Access T = Test Access In the Reset column: S = SRESET H = HRESET M = Module Reset POR = Power On Reset U = Unchanged

Dynamic RAM 4M x 8

Contextual Info: FAST PAGE MODE DYNAMIC RAM 4M x 8 0 £ .M BIT Max. Access Type name time Load memory Outward dimensions Data sheet W x H x D mm page (ns) MH4M08A0AJ-6 ★ 60 M H4M08A0A J-7 ★ 70 MH4M08A0AJA-6 ★ 60 M H4M08A0A JA-7 ★ 70 88.9 x 17.2 x 5.08 M5M417400AJ x 2

free SMD Codebook

Abstract: SMD Codebook RWS 434 RF receiver TDA 1035 a I80386 RDD 17-33 LINEAR INTEGRATE circuit tda 1025 TDA 555 8259A simulator sad1 smd
Contextual Info: ICs for Communications DSP Oriented PBX Controller DOC PEB 20560 Version 2.1 Preliminary Data Sheet 11.97 / e .d s n / e r m o t e si duc . w n w o c w i / / : em p t ht S PEB 20560 Revision History: Current Version: Preliminary Data Sheet 11.97 Previous Version:

Map 6808

Abstract: MAP 6810 motorola 6810 memory C004 MPC555 MPC556 QADC64 INSTRUCTION SET motorola 6800 6058 S 6C46
Contextual Info: APPENDIX A MPC555 / MPC556 INTERNAL MEMORY MAP The tables below use the following notations. In the Access column: S = Supervisor Access Only U = User Access T = Test Access In the Reset column: S = SRESET H = HRESET M = Module Reset POR = Power-On Reset U = Unchanged

sim 300 gsm module VR 0511

Abstract: nf schaltungen PEB 3164 pdsp 2113 halbleiter datenbuch star delta timer siemens siemens cpu 216-2 Siemens Optoelectronic ITT Semiconductors siemens fl 232 v7
Contextual Info: SIEMENS ICs for Communications DSP Oriented PBX Controller DOC PEB 20560 Version 2.1 Contents Overview Functional Block Description Operational Description DSP Core OAK Description of Registers Applications Electrical Characteristics Ordering Information and Mechanical Data

Contextual Info: 67C4500-35/50/65/80 a Deep First-in First-out FIFO 256x9 CMOS Memory DISTINCTIVE CHARACTERISTICS Retransmit capability Expandable In both width an djiepth Increased noise immunity for XI - CMOS threshold RAM based FIFO 256x9 organization Cycle times of 45/65/80/100 nanoseconds

QADC64

Abstract: MPC555 cnh 949
Contextual Info: LIST OF FIGURES Figure Title Page 1-1 1-2 1-3 MPC555 Block Diagram . 1-2 MPC555 Memory Map . 1-6

real time applications of ic 741

Abstract: A1600 GPDS110A1 S200 Ic 741 as I to v converter of 741 ic real time applications
Contextual Info: GPDS110A1 Voice Engine MAR. 14, 2006 Version 1.0 GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. TECHNOLOGY INC. is believed to be accurate and reliable. Information provided by GENERALPLUS However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may

Contextual Info: AT28LV64 Features • • • • • • • • • 2.7 V to 3.6 V Supply Full Read and Write Operation Low Power Dissipation 8 mA Active Current 50 |iA CMOS Standby Current Read Access Time - 200 ns Byte Write - 3 ms Direct Microprocessor Control DATA Polling

Contextual Info: February 1990 Edition 1.0 FUJITSU DATA SHEET M B 8 1 C 1 0 0 1 -7 0 L /-8 0 L /-1 0 L /-1 2 L CMOS 1,048,576 BIT NIBBLE MODE DYNAMIC RAM CMOS 1M x 1 Bit Nibble Mode DRAM The Fujitsu MB81C1001 is a CMOS, fully decoded dynam ic RAM organized as 1,048,576 w ords x 1 bit. T h e MB81C1001 has been designed fo r mainfram e