209L Search Results

Contextual Info: ȕǩȈǤȳǿȩȗǿ 2*161+06'44726'45 LG-209L  Š‫ݡ࢟ٳ‬ඥų&+/'05+105Ტ7PKVOOᲣ 8EE  . .ƸŴ᭗Јщហ‫ٳ‬ႆήȀǤǪȸȉƱŴȕǩȈ᳃ᲽǛ ኵӳǘƤƨᡢᢅ‫׹‬ȕǩȈǤȳǿȩȗǿưƢŵ᭗ࣱᏡŴ᭗ࣱ̮᫂ Ʒཋ˳౨ჷǷǹȆȠƷನ঺ƕܾତưೞ֥Ʒ‫҄׹ݱ‬ǛƸƔǔ

Contextual Info: フォトインタラプタ PHOTOINTERRUPTERS LG-209D 0.8 •外形寸法 DIMENSIONS（Unit : mm） Vcc GND 0.5 0.5±0.1 LG-209L：遮光時ハイレベル出力／High level output at shielding LG-209D：遮光時ローレベル出力／Low level output at shielding

Contextual Info: Product Specification 製品規格 108-79148 4 April 2007 Rev. A1 ＯＭＩ－ＳＳ－２０９Ｌリレー 1 機種・型式 TYPE･MODEL 1.1 適用Ｐ／Ｎ 5-1440001-0 OMI-SS-209L,500 1.2 外形寸法 製品図面による OUTLINE As per Customer Drawing sheet

Contextual Info: フォトインタラプタ PHOTOINTERRUPTERS LG-209L LG-209Lは高出力赤外発光ダイオードと、フォトＩＣを組み •外形寸法 DIMENSIONS（Unit : mm） 合わせた透過型フォトインタラプタです。高性能、高信頼性

MI-SH-209L

Contextual Info: OMI-SH-209L,594 Product Details Mid-Ran ge PC Board Re lays Previous 1 . 6 7 8 9 [10] . 20 Next Alway s EU RoHS compliant but not ELV Compliant Statement of Compliance Quick Links Check Pricing & Availability Search for Tooling Product Feature Selector

BB209

Abstract: CYM52KNP72V33A-10BBC CYM52KNP72V33A-13BBC CYM52KNP72V33A-15BBC
Contextual Info: PRELIMINARY CYM52KNP72AV33 512Kx72 Pipelined MCM with NoBL Architecture Features • No Bus Latency, no dead cycles between write and read cycles • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +5% power supply VDD

100-PIN

Abstract: GVT71256ZC36 GVT71512ZC18
Contextual Info: ADVANCE INFORMATION GVT71512ZC36/GVT71A24ZC18 512K X 36/1M X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS ZBL SRAM PIPELINED OUTPUT 512K x 36 SRAM 1M x 18 SRAM +3.3V SUPPLY, +3.3V or +2.5V I/O FEATURES GENERAL DESCRIPTION • The GVT71512ZC36 and GVT71A24ZC18 SRAMs are

Contextual Info: CY7C1480V33 CY7C1482V33 CY7C1486V33 ADVANCE INFORMATION 2M x 36/4M x 18/1M x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300, 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate

Contextual Info: CY7C1441AV25 CY7C1443AV25 CY7C1447AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • 2.5V core power supply • 2.5V/1.8V I/O power supply

Contextual Info: CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • 3.3V core power supply • 2.5V or 3.3V I/O power supply

CY7C1441AV33

Abstract: CY7C1443AV33 CY7C1447AV33
Contextual Info: CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 PRELIMINARY 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • 3.3V –5% and +10% core power supply (VDD)

CY7C1440AV33

Abstract: CY7C1442AV33 CY7C1446AV33
Contextual Info: CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Pipelined Sync SRAM 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined Sync SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200 and 167 MHz

L1131

Abstract: CY7C1441AV25 CY7C1443AV25 CY7C1447AV25
Contextual Info: CY7C1441AV25 CY7C1443AV25 CY7C1447AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • 2.5V core power supply • 2.5V/1.8V I/O power supply

p055 TRANSISTOR

Abstract: P029H H27 j1 3009 transistor P239 P239 9 318 ITT ZPY ZPY 91 ITT P109t P104t P182C
Contextual Info: & 1-Cube IQ Family Data Sheet Description Features The IQ devices are designed for use in switching and interconnect applications. In switching applications, these devices are used to dynamically switch one or more signals. When used in interconnect applications, the IQ devices

CY7C1441AV33

Abstract: CY7C1443AV33 CY7C1447AV33
Contextual Info: CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1M x 36/2M x 18/512K x 72 common IO ■ 3.3V core power supply ■ 2.5V or 3.3V IO power supply

250ac to 30 v ac

Abstract: CY7C1462V25 CY7C1464V25 CY7C1460V25
Contextual Info: CY7C1460V25 CY7C1462V25 CY7C1464V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns

CY7C1443V33

Abstract: CY7C1441V33
Contextual Info: CY7C1441V33 CY7C1443V33 CY7C1447V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-through SRAM Features • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common I/O • Fast clock-to-output times — 6.5 ns for 133-MHz device — 7.5 ns (for 117-MHz device)

Contextual Info: CY7C1441AV33 36-Mbit 1 M x 36 Flow-Through SRAM 36-Mbit (1 M × 36) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36 common I/O ■ 3.3 V core power supply ■ 2.5 V or 3.3 V I/O power supply ■ Fast clock-to-output times

cy7c1441av33-133axi

Abstract: R1136 CY7C1441
Contextual Info: CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Flow-Through SRAM 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM Features Functional Description • Supports 133-MHz bus operations ■ 1 M × 36/2 M × 18/512 K × 72 common IO

Diagrams

Abstract: 5185143 BG-272 mold cap BG256 BG352 BG-209 Package Diagrams 14X22
Contextual Info: Package Diagrams Ball Grid Array Packages 119-Lead PBGA 14 x 22 x 2.4 mm BG119 51-85115-*A 1 Package Diagrams 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 51-85143-*A 2 Package Diagrams 256-Lead PBGA (27 x 27 x 2.33 mm) BG256 51-85097-*A 3 Package Diagrams 272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272

SAMPLE HOLD

Abstract: CY7C1440V33
Contextual Info: 440V33 CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36 / 2M x 18 / 512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • inputs include all addresses, all data inputs, address-pipelining Chip Enable CE , burst control inputs (ADSC, ADSP, and

BB209

Abstract: bb209 equivalent BWSE CYM26KNP72AV25-10BBC CYM26KNP72AV25-13BBC CYM26KNP72AV25-16BBC CYM26KNP72AV25-20BBC
Contextual Info: PRELIMINARY CYM26KNP72AV25 256K x 72 Pipelined MCM with NoBLTM Architecture Features • No Bus Latency, no dead cycles between write and read cycles • Internally synchronized registered outputs eliminate the need to control OE • Single 2.5V –5% and +5% power supply VDD

CY7C1440AV25

Abstract: CY7C1442AV25 CY7C1446AV25
Contextual Info: CY7C1440AV25 CY7C1442AV25 CY7C1446AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

cy7c1470v25

Contextual Info: CY7C1470V25 CY7C1472V25 CY7C1474V25 ADVANCE INFORMATION 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 300, 250, 200, and 167 MHz • Fast access time: 2.2, 2.4, 3.0, and 3.4 ns