2048KB Search Results

Contextual Info: IßTEXAR X R -T 6 166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The XR-T6166 is a digital CM O S circuit which performs the interface function betweeh a 64kbit/s data stream and a 2048kbit/s PCM timeslot data channel. When

32-PIN

Abstract: DS1249W DS1249W-100 DS1249W-150
Contextual Info: DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation

E99151

Abstract: DS1249W DS1249W-100 DS1249W-100IND MDT32
Contextual Info: 19-5633; Rev 11/10 DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES • •       PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles

MH89793

Abstract: MT8979 MT9079
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

32-PIN

Abstract: DS1249W DS1249W-100 DS1249W-100IND DS1249W-150 DS9034PC DS9034PCI
Contextual Info: DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation

Contextual Info: MH89792 MITEL E1 Line Interface Unit LIU Preliminary Information Features • ISSUE 4 Complete prim ary rate 2048kbit/s E1 line driver and receiver with clock recovery MH89792-1 MH89792-2 Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transm it and

Contextual Info: J T E X A R XR-T6165 Codirectional Digital Data Processor PIN ASSIGNMENT GENERAL DESCRIPTION The XR-T6165 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in

clock alarm circuit diagram

Contextual Info: 22* E X 4 R XR-T6166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The XR-T6166 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in

Contextual Info: DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation

MH89793

Abstract: MT8979 MT9079
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

MH89793

Abstract: MT8979 MT9079 zarlink PDIP
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

Contextual Info: MH89792 E1 Line Interface Unit LIU Data Sheet Features DS5712 Issue 4 March 2002 Ordering Information • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery • Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and

MH89792

Abstract: MH89792-1 MH89792-2 MT8979 MT9041 MT9079 PCM30 RJ48C
Contextual Info: MH89792 E1 Line Interface Unit LIU Data Sheet Features DS5712 Issue 4 March 2002 Ordering Information • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery • Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and

Contextual Info: EX4R XR-T6165 Codirectional Digital Data Processor PIN ASSIGNMENT GENERAL DESCRIPTION The XR-T6165 is a digital CMOS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM timeslot data channel. When used in conjunction with the XR-T6164, the XR-T6165 conforms

Contextual Info: E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features ISSUE 2 • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery • Meets ETSI requirements [ETSI ETS 300 011, NET 5] • Built-in selectable term ination impedance

Contextual Info: XR-T6166 Codirectional Digital Data Processor FUNCTIONAL BLOCK DIAGRAM G EN ERA L DESCRIPTION The XR-T6166 is a digital CM OS circuit which performs the interface function between a 64Kbit/s data stream and a 2048Kbit/s PCM tim eslot data channel. When used in

MH89792

Abstract: MT9079 PCM30 RJ48C MH89792-1 MH89792-2 MT8979 MT9041 TPEC
Contextual Info: MH89792  E1 Line Interface Unit LIU Preliminary Information ISSUE 4 Features • • • • • • • • • Complete primary rate 2048kbit/s E1line driver and receiver with clock recovery Meets ETSI requirements (ETSI ETS 300 011, NET 5) Onboard pulse transformers for transmit and

MH89793

Abstract: MT8979 MT9041 MT9079 PCM30 RJ48C RZA 18 RJ48
Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information  Features ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

square root extractor

Abstract: RXB 24 MH89792 MH89792-1 MH89792-2 MH89792-3 MT8941 MT8979 MT9042 MT9079
Contextual Info: MH89792  E1 Transceiver Preliminary Information Features ISSUE 3 April 1995 Ordering Information • Complete primary rate 2048kb/s CEPT line driver and receiver MH89792-1 MH89792-2 MH89792-3 • Onboard pulse transformers for transmit and receive • Meets latest ETSI requirements ETSI ETS 300

square root extractor

Contextual Info: @M|TEL MH89792 E1 Transceiver Preliminary Information O rdering Inform ation • Com plete prim ary rate 2048kb/s CEPT line driver and receiver • O nboard pulse transform ers fo r transm it and receive • Meets latest ETSI requirem ents ETSI ETS 300 011 (NET 5

Zarlink Pin Compatible

Contextual Info: MH89793 E1 Line Interface Unit LIU with Selectable Impedance Preliminary Information Features DS5419 ISSUE 2 June 1996 Ordering Information • • • • • • • • Complete primary rate 2048kbit/s E1 line driver and receiver with clock recovery Meets ETSI requirements [ETSI ETS 300 011,

square root extractor

Abstract: 6 pin pulse transformer MH89793 120R MT9042 MT9079 PCM30 E1 frame square root extractor application
Contextual Info: MH89793  E1 Transceiver with Selectable Impedance Preliminary Information Features ISSUE 1 April 1995 Ordering Information • Complete primary rate 2048kb/s CEPT line driver and receiver MH89793 28 Pin DIL Package Surface Mount Option is available by adding

Contextual Info: DS1249W 3.3V 2048kb Nonvolatile SRAM www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation