2 WAY ASSOCIATIVE Search Results

Contextual Info: MB86932_ FUJITSU 930 Series 32-BIT RISC EMBEDDED PROCESSOR M AY 25, 1994 FEATURES • 4 0 MHz 25ns/cycle operating frequency • SPARC high performance R ISC architecture • 8 Kbytes 2-way set associative instruction cache • 2 Kbytes 2-way set associative data cache

KM78C80

Contextual Info: PRELIMINARY CMOS SRAM KM78C80 8 K X 16 /4 K X 16X2-Way Cache Data Static RAM FEATURES DESCRIPTION • Configurable for 2-Way or Direct Mapped Cache Organizations -2-way: 4,096 words x 16 bits — Direct: 8,192 words x 16 bits • On-Chip Address Latches for A0-A11

Contextual Info: MB86932 FUJITSU SPARCIite 32-BIT RISC EMBEDDED PROCESSOR MAY 25, 1994 FEATURES • 4 0 M H z 2 5 n s/cy cle operating frequency • SPARC high perform ance R IS C architecture • 8 K by tes 2 -way set associative instruction cach e • 2 K bytes 2 - way set associative data cache

Contextual Info: 4flE D HÖSEL — VITELIC m bBSaaTl OOGlDbl 7 • UOVI Product Brief MOSEL .«.„„« a*« MS82C340 Cache Chipset for 80386 Systems with Write-Back Cache FEATURES T -4 6 -2 3 -1 4 Direct mapped, 2-way and 4-way set associative cache mapping options supported

block diagram of 80386 microprocessor

Abstract: 80386 microprocessor features block diagram of processor 80386 interface 80386 80387 80386 bus technology
Contextual Info: MOSEL Product Brief MS82C340 Cache Chipset for 80386 Systems with Write-Back Cache FEATURES Highly integrated VLSI components offer complete cache solution - MS82C341 Cache Controller - MS82C342 Expansion Tag RAM - MS82C343 Quad Data RAM Direct mapped, 2-way and 4-way set associative cache

i960 Cx Instruction Set Quick Reference

Abstract: I960 hx i960 Cx Processor Instruction Set Quick Reference 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA 80960JD
Contextual Info: i960 HA/HD/HT Superscalar Microprocessors PRODUCT HIGHLIGHTS • Superscalar RISC core ■ 16 Kbyte four-way set associative instruction cache ■ 8 Kbyte four-way set associative data cache ■ 2 Kbyte on-chip data RAM ■ On-chip high-speed interrupt controller

Audacity-T2U

Abstract: MIPS microprocessor databus BGA PROFILING FOIP Netergy Microelectronics DMA engine
Contextual Info: Audacity-T2U Processor Features lNetergy Microelectronics' MIPS-X5 unified RISC and DSP core up to 180 DSP MIPS lPin and code compatible with the Audacity-T2 processor l384 KByte on-chip RAM, 16-way interleaved with single cycle access l16 KByte, 2-way set associative

Contextual Info: SN74BCT2160 8K X 4 2-WAY CACHE ADDRESS COWIPARATOR/DATA RAM D 3512, JU NE 1990 FM PACKAGE TOP VIEW LO ^ n w r o < < < < < < Fast Address to Match Time . . . 12 ns Max 2-Way Architecture Significantly Improves Hit Rate 4 * Implements LRU Replacement Algorithm

Audacity-T2

Abstract: Netergy Microelectronics 49258 voip ethernet single chip 256 kbyte Low Power Serial SRAM Master Of The House Netergy BGA 15x15mm DMA engine J-Squared Technologies
Contextual Info: Audacity-T2 Processor Features Netergy Microelectronics' MIPS-X5 unified RISC and DSP core 150+ DSP MIPS 256 KByte on-chip RAM, 8-way interleaved with single cycle access 4 KByte, 2-way set associative read-only cache for external FLASH/SRAM memory External memory-mapped bus

BCM4320

Abstract: BCM4318 BCM4321 BCM4309 BCM4705 BCM5397 BROADCOM BCM4320 Broadcom WLAN BCM4318 2x2 MIMO block diagram diagram of wifi wireless router
Contextual Info: BCM4705 Brief Intensi-fi Gigabit Ethernet Draft-802.11n Processor SUMMARY OF BENEFITS FEATURES • Advanced 500 DMIPS/300-MHz MIPS32® core • • • • 4-way set associative 32-KB I-Cache 2-way set associative 32-KB D-Cache 4-KB Read-Ahead Cache

8kx1 RAM

Abstract: SN74BCT216012 D3512 SN74ACT2160 SN74BCT2160-12
Contextual Info: SN74BCT2160 8K x 4 2-WAY CACHE ADDRESS COMPARATOR/TAG RAM SCHS011 - D3512, JUNE 1990- REVISED MARCH 1992 Fast Address to Match Time. . . 12 ns Max IO Upgrade of the SN74ACT2160 FM PACKAGE TOP VIEW o • 't CO OJ 1- o < < < < < < Q 2-Way Architecture Significantly Improves

HM62A168

Abstract: 8d15 62A168
Contextual Info: HM62A168/HM62A188 Series Prelim inary • PIN-OUT Direct M apped 8,192-Word x 16/18-Bit 2-Way 4,096-W ord x 16/18-Bit Static Cache RAM ■ DESCRIPTION T h e Hitachi H M 62 A 168 /H M 62A 1 88 is a high speed 128/144-kbit static cache RAM organized as 2-way set associative 4k x 16/18 or

SDRAM edac

Abstract: AT697 Radiation report AT697 AT697E AT697F SPARC T4-2 at697e-2h-e MQFP256
Contextual Info: Features • SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows • Advanced Architecture: • • • • • • • • • • • • – On-chip Amba Bus – 5 Stage Pipeline – 32 KB 4-way associative Instruction Cache – 16 KB 2-way associative Data Cache

5962-0722402vyc

Abstract: AT697F bootstrap AT697F 5962-0722402QYC ufc 101 vc 5962R0722402VYC AT697F-KG-E SDRAM edac 5962-0722402QXB MCGA349
Contextual Info: Features • SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows • Advanced Architecture: • • • • • • • • • • • • – On-chip Amba Bus – 5 Stage Pipeline – 32 KB 4-way associative Instruction Cache – 16 KB 2-way associative Data Cache

D3365

Abstract: SN74ACT2160
Contextual Info: SN74ACT2160 8K x 4 2-WAY CACHE ADDRESS COMPARATOR/DATA RAM D3365, JANUARY 1990-REVISED JUNE 1990 Address to Match Time . . . 1 7 n s Max FM PACKAGE TOP VIEW 2-Way Architecture Significantly Improves Hit Rate KT> CO C\J 1 - O < < < < < < O O y L J P C J L J L J a n

HM62A168CP-25

Abstract: HM62A168 HM62A188CP25R
Contextual Info: HM62A168, HM62A188 Series-Direct Mapped 8,192-Word x 16 18 -Bit/ 2-Way 4,096-Word x 16(18)-Bit Static Cache Memory • DESCRIPTION The H itachi H M 62A168/188 is a high speed 128(144)-k Cache memory organized as 2-way set a sso cia tive 4k x 16(18) or direct m apped 8k x

SN74BCT2160

Contextual Info: SN74BCT2160 8K X 4 2-WAY CACHE ADD REÍSS COMPARATOR/DATA RAM D 3 5 1 2 , A U G U S T 1990 - R E V IS E D A U G U S T 1990 FM P A C K A G E Fast Address to Match Time . . . 12 ns Max CTOP V IE W in < < 2-Way Architecture Significantly Improves Hit Rate <

MB86930-20PFV-G

Abstract: QFP-208 fujitsu mb86901
Contextual Info: MB86930 FUJITSU SPARCIite 32-BIT RISC EMBEDDED PROCESSOR May 25, 1994 FEATURES_ • 4 0 MHz 25ns/cycle operating frequency • SPARC high-performance R ISC architecture • 2 Kbytes 2-way set associative instruction cache •

mb81c51

Contextual Info: cP February 1990 Edition 2.0 - - DATA S H E E T FUJITSU MB81C51-2S/-30 CMOS TAG RANDOM ACCESS MEMORY CMOS Tag Random Access Memory The Fujitsu MB81C51 is a 512 entry x 4 way or 1024 entry x 2 way tag random access memory Tag RAM fabricated with CMOS technology.

MN103E0600YD

Abstract: SD21 SD27 SD31
Contextual Info: MN103E0600YD Type MN103E0600YD Instruction Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Minimum Instruction Execution Time Interrupts • XIRQ x 8 • NMI • Timer × 14 • DMAC × 4 • WDT • SIO × 6 • I2C × 2 • Asynchronous bus error

SN74ACT2160

Abstract: D3365
Contextual Info: SN74ACT2160 8K X 4 2-WAY CACHE ADDRESS COMPARATOR/DATA RAM D3365, JA N U A R Y 1 9 90-R E V IS E D JU NE 1990 Address to Match Time . . . 17 ns Max FM PACKAGE TOP VIEW 2-Way Architecture Significantly Improves Hit Rate IO t O W T- O O < < < < < < O I II II II II II II I

HM62A168

Contextual Info: HM62A168, HM62A188 Series Direct Mapped 8,192-Word x 16 18 -Bit/ 2-Way 4,096-Word x 16(18)-Bit Static C ach e Mem ory • DESCRIPTION The H itachi H M 62A168/188 is a high speed 128(144)-k Cache memory organized as 2-way set a sso cia tiv e 4k x 16(18) or dire ct m apped 8k x

intel 82385

Abstract: 82386 20D11 21G22
Contextual Info: SN74ACT2140A 2-WAY 4K x 18/8K x 18 CACHE DATA RAM D3291, N O VEM BER 1989-R E V IS E D JUN E 1990 FN P ACKA G E Interfaces Directly with the Intel 82385 Cache Controller TOP VIE W T - C M C O T j-in tO I II II 6 II 5 AO ] 8 7 GND ] 9 Configurable for 2-Way or Direct Mapped

Contextual Info: #U209 H M 644332 GMICRO TAGM 2k Entiy Tag Memoiy for Cache System Preliminary SEPTEMBER, 1989 0 H IT A C H I The HM644332 TAGM is a 2048-entry tag m emory fabricated with CMOS technology. It supports compact cache systems with 2-way or 4-way set associativity and a high level of perform ance for