1Q14 Search Results

456DB-1007

Contextual Info: ! type 182 ! B7T rSJTOKO Baiun Transformers TYPE B7T: Leaded 5-0O.5PIN 3ÌÌ TT 2 è ^É â à k j Ahh L ij] 6 □ 4 .5 Un:t: mm STANDARD TRANSFORMERS SELECTION GUIDE TYPE B7T TOKO Part Number Number of turns per W inding Double Balanced Mixer 456DB-1013 456DB-1Q14

15-V

Abstract: SN74HSTL162822
Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091 A - D ECEM B E R 1996 - R EVISED A P R IL 1997 Member of the Texas Instruments Widebus Family DGG PACKAGE TOP VIEW Inputs Meet JEDEC HSTL Standard JESD8-6 1Q2 [ , 2Q1 [ 2 1Q1 [ 3

Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

YAG-100A

Abstract: 7052 glass MIL-STD-750b YAG-200 YAG100A YAG-100 YAG-444 YAG-040B YAG040B
Contextual Info: E G & G S7E JUDSON D • B030b0S 0G0Q177 M ■ YAG Series Features • • • • • • • • • Planar Diffused Large Area Wide Dynamic Range > 5 0 % DC Quantum Efficiency at 1064 nm Pulse Quantum Efficiency at 1064 nm > 3 8 % at 20 nS Pulse Width Oxide Passivated

P4950

Contextual Info: Si PIN Photodiodes 5 Type No. I Dimensional Outline (P.49, 50)/ Window Material *1 Package (mm) S5106 /R Ceramic S5107 @ /R Chip-carrier 57509 ; ; Active Effective j Active Area Size; Area ! 5 x 5 10 x 10 j : 2xio ® r ; (mm2) Spectral Response Range

Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

Contextual Info: LOGIC DEVICES INC at.E D • S5b5TQS O O O U O b 2 ■ T -9 é ~ 2 3 -a sr 64K x 1 Radiation-Hard Static RAM FEATURES □ 64K x 1 Radiation-Hard Static RAM with Separate I/O , Chip Select Powerdown □ Address Access Time: £ 5 0 n sat8 0 °C □ Total Dose: £10* Rads Si02

LTS23305

Abstract: HP 5082-7653 LTD-585G CSS-517Y LTD482RC CSM-57442E HDSP-3403 MAN3920A LTS-4540-AG tdso 5160 k
Contextual Info: Cross Reference For detailed comparison, please always refer to m anufacture r's specs Manufacturer Part Number CSC P/N A B C HP 50 82 -761 0 CSS-3126-11 X X X HP 5 0 8 2-7 6 1 1 CSS-31 2E 1 1 X X X D j 0.30 F" C f ’t ‘ G " C p N •- 0 .3 0 r~ 'i j N

FZH 121

Abstract: cdb 400E 74LS042 fzh 141 TDA+7450 fzh 115 FZH 111 CDB411HE FZH 131 FZH 171
Contextual Info: INTEGRATED CIRCUITS ALPHANUMERIC CDB 400E, EM_ .26 CDB 400HE, HEM. .26 CDB 402E.EM_ .26 CDB 403E.EM_ .26 CDB 404E.EM_ .26 CDB 405E.EM_ .26 CDB 406E,EM_ .26 CDB 407E.EM_ .26 CDB 408E.EM_ .26 CDB 4Q9E.EM_ .26 CDB 410E.EM- .26 CDB 410HE.HEM.26

Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

51L33

Contextual Info: INTEGRATED TO SH IB A CIRCUIT TECHNICAL TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT DATA TC9309AF SILICON MONOLITHIC SINGLE CHIP DTS MICROCONTROLLER DTS-10 The TC9309AF is a 4bit CMOS microcontroller for single chip digital tuning system with built-in prescaler, PLL and

Contextual Info: HITACHI/ -CUNEAR DEVICES} 5t.E D 44 T taSO 5 0010=143 & HA11508- T - ' » 07-07 Audio-Video Switch H A 11508 is an input signal sw itching IC designed for use Features in c olo r televisions w ith ex tern al input term inals. H A 11508 provides sw itching operations fo r three video

MCF5206

Abstract: RC10 RC11 00FE0000
Contextual Info: SECTION 10 DRAM CONTROLLER 10.1 INTRODUCTION The DRAM controller DRAMC provides a glueless interface between the ColdFire core and external DRAM. The DR a M c supports two banks of DRAM. Each DRAM bank can be from 128 kbyte to 256 Mbyte. The D r A m C can support DRAM bank widths of 8, 16, or 32

Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

Contextual Info: C U R R E N T LIM ITING a p É x . M l C R O T e C H H O L O C Y APPLICATION NOTE 9 POW ER O PERATIO N AL AM PLIFIER h t t p ://WWW.APEXMICROTECH.COM 80Q 546-APEX (800) 546-2739 INTRODUCTION Power op amp circuits without suitable current limiting can be

EBC91

Abstract: BA871
Contextual Info: 12345657 1 7 1 9E979AF8FCE7 71 61 91 71 87791 77B1 A1 6789ABC91 61 !"C1 A1 EBAEA8BA""7B91 1 A8E#1 9#77E1 D$%1 E!#!"79F1 71 61 !91 !8C1 7!&B791 A1 71 635'1 &1 B7 &E7(1 81 EA91 C1 

15-V

Abstract: SN74HSTL162822
Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

15-V

Abstract: SN74HSTL162822 1Q14 LE1451
Contextual Info: SN74HSTL162822 14-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091 - D ECE M B ER 1996 DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD 8-6 1Q2 [ , 2Q1 [ 2 1Q1 [ 3 GND [ 4 D1 [ 5 D2 [ 6 D3 [ 7 All Outputs Have Equivalent 25 -Q. Series

15-V

Abstract: SN74HSTL162822
Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

mk22fn

Abstract: KE06
Contextual Info: TM August 2013 • Kinetis Portfolio - Baseline • Kinetis K – CSP Packaging • Kinetis K – Security Expansion • Kinetis K - Memory Expansion • Kinetis K – FPU Expansion • Kinetis L - Low Power • Kinetis E - 5V Robust • Kinetis V – Motor Control

74150

Abstract: 18E DBM panasonic resistors ERA marking code CH1770 CH1765-01 fsk modem 1200 HM6116 interface z 80 with 8251a usart marking code 1AW 74LS374 74LS373 74ls373
Contextual Info: CERÍ1ETEK M I C R O E L EC TR ON IC S IflE D 1 7 0 0 • EQ05flD3 5 ■ S E R I E ST-75 -33-05 Cermetek mtoroatootronlo« 130» B O * IE O A » A V I SU M N YY A lt CA •<««« T lL .U 0 * t 7 t a - W « CH1765 » 6 0 / 1 2 6 0 BA U D IM T K lL t& tM T tftODCM

15-V

Abstract: SN74HSTL162822
Contextual Info: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series

CMOS Data Book Texas Instruments Incorporated

Abstract: SN74ALB16244 SN74ALB16245 SN74ALVC00 SN74ALVC04 SN74ALVC08 SN74ALVC10 SN74ALVC125 SN74ALVC14 SN74ALVC32
Contextual Info: General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data Output Derating Curves A ALVC Advanced Low-Voltage CMOS Data Book Including SSTL, HSTL, and ALB