A21D Search Results

Contextual Info: □ Mini-Circuits l&Q Demodulators good amplitude and phase unbalance 1.15 MHz to 895 MHz MIQY MIQC FREQUENCY M H z M O D EL NO. M IQ A-10D M IQ A-21D M IQ A-70D M IQ C-895D <<< A ZFMiQ-lOD A ZFMIQ-70D A ZAMIQ-895D □ MIQY-1.25D □ MIQY-70D □ MIQY-140D

1j63

Abstract: .1J63 7062l
Contextual Info: f QE1F-PIus Device f t r H Quad E1 Framer-Plus TXC-03114 DATA SHEET DESCRIPTION The QE1F-Plus is a four-channel E1 2048 kbit/s framer designed for voice and data communications applications. A dual unipolar or NRZ line interface is supported with full alarm detection and generation per

uPD72103AGC-3B9

Abstract: uPD72103A uPD72103 uPD7210 UPD72103AGC uPD70116 uPD71059 S10766E UPD72103ALP
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD72103A HDLC CONTROLLER DESCRIPTION The µPD72103A HDLCC High-Level Data Link Control Procedure Controller is a communication control LSI which supports HDLC. Since the HDLCC has an on-chip DMA (Direct Memory Access) function, the host system can perform serial

s12w

Abstract: PDC 140M PLP-21.4 S-40W s40w T560N T1-1-KK BA25L
Contextual Info: Model Index D o t in d ic a t e s s u r fa c e m o u n t m o d e ls . mixers m odel A D E 'l . ADE-l A S K . AD E-l H . A D E -IH W . AD E-l L . A D E 'l LH . A D E 'IL H W .

CH341A

Abstract: 03104 bilq AMI 52 732 V TS16 TXC-03114 national alarm RFTS-10 X77H-X70H
Contextual Info: QE1F-Plus Device Quad E1 Framer-Plus TXC-03114 FEATURES DESCRIPTION • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode • Frame alignment detection and loss of frame

B17C

Abstract: 4202 bd datasheet BD 139 N A13B A5l102 A18E 48-7191 A17A 48-2210 AND501
Contextual Info: PIN NUMBER 2161-1 102 PIN LENGTH 19.0/.750 PLATING 102 MATING “M” 11.43/.450 PCB “P” 4.37/.172 GOLD “G” N/A TIN “T” OVERALL PACKAGING PK-41661-001 STATUS A-41661-ANA102-* MATERIAL ENGINEERING VOIDS 26-48-1021 26-48-1031 26-48-1041 26-48-1051

B22Y

Abstract: A08K B15Y 26-48-1082 b10y A14K A09K
Contextual Info: HEADER NUMBER: PIN NUMBER: PLATING PIN LENGTH: L MATING LENGTH: X GOLD POINT: G PIN HEIGHT: Y PC TAIL LENGTH: Z TIN: T CKTS: VOIDED CKTS: PACKAGING: MATERIAL ENG NUMBER NUMBER 26-48-1022 -A02A102 26-48-1032 -A03A102 26-48-1042 -A04A102 26-48-1052 -A05A102

PD72103

Abstract: CS 1602 B IPD7210 UPD72103 PD72103A
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT HDLC CONTROLLER DESCRIPTION The ¿¡PD72103A HDLCC High-Level Data Link Control Procedure Controller is a communication control LSI which supports HDLC. Since the HDLCC has an on-chip DMA (Direct Memory Access) function, the host system can perform serial

CH341A

Abstract: digital trainer schematic diagram laf 0001 CH3401 J0123 ccs ldl HP 3D6 000A75 X77H-X70H TO SI 788 48D
Contextual Info: H i/1 I - = - ^ • QE1F Device Quad E1 Framer TXC-03104 DATA SHEET FEATURES DESCRIPTION • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and

76 COC 9K

Abstract: VIP 22A 2048KHZ 44145 ch3406
Contextual Info: QE1F Device Quad E1 Framer TXC-03104 DATA SHEET FEATURES DESCRIPTION ^ * Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode * Frame alignment detection and loss of frame

TIC147

Contextual Info: E1 Fx8 Device a n 8-Channel E1 Framer TXC-03109 X-S w i t c h DATA SHEET PRODUCT PREVIEW DESCRIPTION FEATURES Eight-channel offline framer supports standard and frame hold-off frame alignment with CRC-4 multiframe check, selectable out of frame criteria and change of frame

Contextual Info: QE1F Device Quad E1 Framer TXC-03104 DATA SHEET FEATURES DESCRIPTION = • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode • Frame alignment detection and loss of frame

HP900

Abstract: NAT-1 3M S11A jl6g MAN1A STRM-50 ZHL-4240 NP300 mav-3sm BLP-10.7
Contextual Info: Model Index • D ot indicate s surface m o u rt models. mixers • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

A21D

Contextual Info: D em odulators ▲ ZFMIQ-70D ▲ ZAMIQ-895D 9 20 66 20 11 23 73 60 DC DC DC DC 9 66 868 n 73 895 67 137 73 143 Typ. Max. Plug-In & Coaxial HARMONIC SUPPRESSION <-dBc 3XÌ/Q Typ. Min. 5XI/Q Typ. Min. CAM STYLE C N N t Ç T PRiCE Q N Oty. <1-9) i Note B i x

A08K

Abstract: B15Y A14K A02K B22Y A17a b10y A23AB A13B1 A04A
Contextual Info: HEADER NUMBER: PIN NUMBER: PLATING PIN LENGTH: L MATING LENGTH: X GOLD POINT: G PIN HEIGHT: Y PC TAIL LENGTH: Z TIN: T CKTS: VOIDED CKTS: PACKAGING: MATERIAL ENG NUMBER NUMBER 26-48-1022 -A02A102 26-48-1032 -A03A102 26-48-1042 -A04A102 26-48-1052 -A05A102

Contextual Info: E1Fx8 Device 8-Channel E1 Framer TXC-03109 FEATURES DESCRIPTION • Eight-channel offline framer supports standard and frame hold-off frame alignment with CRC-4 multiframe check, selectable out of frame criteria and change of frame alignment alarm, plus transparent non-framing mode

VIP 22A

Abstract: BC 4E7 ch341a 2048KHZ SS125 AMI 1108 ch3406
Contextual Info: QE1F Device Quad E1 Framer TXC-03104 DATA SHEET DESCRIPTION = • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode • Frame alignment detection and loss of frame

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT H P D 7 2 Ì 0 7 LAP-B CONTROLLER Link Access Procedure Balanced mode The ¿¡PD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single chip. FEATURES • Complied with ITU-T recommended X.25 LAP-B84

Contextual Info: tm ä n S w it c h „ QE1F Device Quad E1 Framer TXC-03104 X- DATA SHEET FEATURES DESCRIPTION • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode

Contextual Info: MITSUBISHI LSIS M5M4V16400CJ,TP-5,-6,-7, -5S,-6S,-7S FAST PAGE MODE 16777216-BIT 4194304-WQRD BY 4-BIT DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is a fam ily of 4194304-word by 4-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal

PD72107

Abstract: SSL110 uPD7210 PD98201 uPD98201 PD7210 UPD70116 uPD71059 PD72107L
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD72107 LAP-B CONTROLLER Link Access Procedure Balanced mode The µPD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single chip. FEATURES • Complied with ITU-T recommended X.25 LAP-B84

uPD72001 users manual

Abstract: uPD72001 manual PD72001 d70116 d71059 uPD7210 uPD72103 S10766E d71082 PD72103
Contextual Info: µPD72103A HDLC CONTROLLER µPD72103A 1997 Document No. S10766EJ9V0UM00 9th edition Date Published March 1997 N CP(N) Printed in Japan NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

Contextual Info: QE1F-Plus Device tmän S w it c h Quad E1 Framer-Plus TXC-03114 x- FEATURES DESCRIPTION • Offline framer supports Standard and Frame HoldOff frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode

Contextual Info: QE1F Device Quad E1 Framer TXC-03104 DATA SHEET • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode • Frame alignment detection and loss of frame