19B7 Search Results

Contextual Info: SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056A - D2932, MARCH 19B7-REVISED OCTOBER 1993 • Internal Look-Ahead Circuitry for Fast Counting • Carry Output for N-Bit Cascading D OR N PACKAGE TOP VIEW • Fully Synchronous Operation for Counting • Package Options Include Plastic

Contextual Info: TICHALI 6L8-35C, TICHALI 6R4 35C, TICHAL16R6 35C, TICHALI6R8-35C HIGH SPEED H A I CIRCUITS D 2 9 7 2 , MARCH 1 9 8 7 - R E V IS E D DECEM BER 19B7 Mask-Programmed Version of 20-Pin PAL’ Family TIC H A L 1 6 L 8 C SU F FIX . . . DW OR N P A C KA G E TO P VIEW

Contextual Info: TIBPALT19L8M, TIBPALT19R4M, TIBPALT19R6M, T1BPALT19R8M TIBPALT19L8C, TIBPALT19R4C, TIBPALT19R6C, TIBPALT19R8C HIGH PERFORMANCE REGISTERED-INPUT PAL CIRCUITS D 2709, DECEMBER 1982 —REVISED DECEMBER 19B7 • • High-Performance Operation . . . 3 0 MHz 9 DIP Options Include Both 300-mil Plastic

Contextual Info: SN54F56B, SN54F569, SN74F568, SN74F569 SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS □2 9 32 , MARCH 19B7-REVISED JANUARY 1989 • S N 5 4 F 5 6 8 , S N 5 4 F S 6 9 . . . J P AC KAG E S N 7 4 F 5 B 8 . S N 7 4 F 5 6 9 . . . D W OR N PAC KA G E

RJ89

Abstract: 50721
Contextual Info: FORM Sr.P a I 1 93 D IS T R IB U T IO N S T A T E M E N T A. o u S G O V W N M IN T PRINTING OFFICE 19B7 — 748 129/60911 5962-El 190 A p p ro v e d lo r p u b lic re le a s e ; d is trib u tio n Is u n lim ite d . 1. SCOPE 1.1 Scope. T h is drawin g d e s c r ib e s d e vic e re q u ire m e n ts f o r c la s s B h y b r id m i c r o c i r c u i t s t o be

Contextual Info: TCM129C18, TCM129C19, TCM29C18, TCM29C19 ANALOG INTERFACE FOR DSP D3036. AUGUST 19B7-REVISED JUNE 1988 N DUAL-IN-LINE PACKAGE TOP VIEW I Low Power Consumption Operating Mode . . . 80 mW Power-Down Mode . . . 5 mW 71-Law Coding vbb C 1 U ie D v c c PW RO + C 2

SN54F568

Abstract: rtl decade counter SN54F569 SN74F568 SN74F569 EN10
Contextual Info: SN54F568, SN54F569, SN74F568, SN74F569 SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS □2 9 32 , MARCH 19B7 —REVISED JANUARY 1989 • 3 -S ta te Q O u tp u ts D rive Bus Lines D irectly • C o u n ter O p eration In de p e n d e n t o f 3 -S ta te

TG 346

Abstract: HC151 SN54HC251 SN74HC251
Contextual Info: SN54HC251, SN74HC251 DATA SELECTORSfMULTIPLEXERS WITH 3-STATE OUTPUTS D 2 6 8 4 . DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 19B7 S N 5 4H C 25 1 . . . J PA CK A G E SN 74H C 251 . . . D OR N PA CKAG E TOP VIEWI High-Current 3-State Outputs Interface Directly with System Bus or Can Drive Up

Contextual Info: FU JITSU September 19B7 Edition 1.0 FREQUENCY-TO-VOLTAGE CONVERTER The Fujitsu MB4206 Is a frequency-to-voltage converter with an on-chlp com parator. The M84206 uses a charge pump driven by a posltive-edge Schm itt trigg e r/flip -flop Input so stable operation Is achieved against noise

et 312

Abstract: z3mm
Contextual Info: REVISIONS RELEASED. E.C.J. A ? fi. 9 . 19B7 RED R A H N . A JC C C D W N EW fORMAT. DGW 1 - 1 0 -2 9 Ü 2 PDF File Made ï “" a. 5 3 o Pio 3as !Jti jII e • K. O o z S JO > X ¥r d cn M g !►I 4"° gm ïï 33 s to ~T], a5 1? CT>? to I o> o 0,1 I > CO w

Contextual Info: 54ACT11640, 74ACT11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0094— D2957, JULY 19B7— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54ACT11640 . . JT PACKAGE 74ACT11640 . . . DW OR NT PACKAGE Flow-Through Architecture to Optimize PCB

Contextual Info: SN54F10, SN74F10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDFS039A - MARCH 19B7 - REVISED OCTOBER 1993 Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs SN54F10 . . . J PACKAGE SN74F10 . . . D OR N PACKAGE

19B7

Abstract: econoseal
Contextual Info: DO NOT SCALE DIM ENSIO NS ÍN MM. d> - 2 > 3 0 . 50 70. 80 S E C T IO N ^COPYRIGHT 19B7BY AMP o f SRCAr . IwTÉfiNAriONAL RIGHTS RFSfftVEO. J.LL PftÛOIXîrS |_ f CDVÉftfD Bf BRrrJSH AND fùff£JGWPATÊN7S ANÛ/Ofl 2-2 NO TES; T H IS TO APPLY SHROUD.

D2967

Abstract: 74ACT11032 D2957 364Bh 54ACT11032
Contextual Info: 54ACT11032, 74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TP0061 —D2957, JULY 19B7—REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54ACT11032 . . . J PACKAGE 74ACT11032 . . . D O R I 4 PACKAGE Flow-Through Architecture to Optimize PCB Layout

Contextual Info: SN54HC283, SN74HC283 4 BIT BINARY FULL ADDERS WITH FAST CARRY D 2 8 0 4 , M AR C H 1 9 8 4 —REVISED SEPTEMBER 19B7 Full-Carry Look-Ahead Across the Four Bits • Systems Achieve Partial Look-Ahead Performance with the Economy of Ripple Carry S N 5 4 H C 2 8 3 . . . J P AC KA G E

Contextual Info: SN54BCT620A, SN74BCT620A OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SC8S001B - SEPTEMBER 19B7 - REVISED NOVEMBER 1993 SN54BCT6Z0A . . . J OR W PACKAGE SN74BCT620A . . . DW OR N PACKAGE TOP VIEW State-of-the-Art BiCMOS Design Significantly Reduces l^cz P-N-P Inputs Reduce DC Loading

Contextual Info: 1 1 1 1 1 46 !"6 1 ◆1 CD39E6F6A1 ・ ・

Contextual Info: 1 1 1 1 1 46 !6 1 ◆1 CD39E6F6A1 ・ ・

C4515

Abstract: 54HC4514 C4514 a 4514 v C451-4 hc451 54HC4515
Contextual Info: SN54HC4514, SN54HC4515, SN74HC4514, SN74HC4515 4-LINE TO 16-LINE DECQDERSfDEMULTIPLEXERS WITH ADDRESS LATCHES 0 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 19B7 • T w o Output Options: 'H C 4 5 1 4 H as Active-H igh Outputs 'H C 4 5 1 5 Has A ctive-Low Outputs

sn74f114

Contextual Info: SN 54F114, S N 7 4 F1 14 DUAL J K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK D2932, MARCH 19B7 —REVISED JA N U A R Y 1989 SN54F114 Package Options Include Plastic "S m a ll SN74F114 O utline" Packages, Ceram ic Chip Carriers,

Contextual Info: SN54F620 THRU SN54F623, SN74F620 THRU SN74F623 OC TAL BUS TRANSCEIVERS 02932, MARCH 19B7— REVISED JANUARY 1989 Local Bus-Latch Capability SN54F' J PACKAGE S N 74' . . . DW OR N PACKAGE Choice of Inverting or Noninverting Logic TOP VIEW Choice of 3-State or Open-Collector Outputs

74AS260

Contextual Info: SN74AS250A, SN54AS250A 1-0F-16 DATA GENERATORS/MULTIPLEXERS WITH 3-STATE OUTPUTS D2910, DECEM BER 1983 - REVISED JU NE 19B7 * 8 N S 4 A S 2 S 0 A . . . JT PACKAG E' 8 N 7 4 A S 2 6 0 A . . . O W OR NT PA C K A G E 4-Lhte to 1-Une Multiplexer that Can Salact

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0071— D2957, JULY 19B7— REVISED MARCH 1990 54AC11241 . . . JT PACKAGE 74AC11241 . . . DW OR NT PACKAGE 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers TOP VIEW

54AC11008

Abstract: 54AC11008/B2A
Contextual Info: 54AC11008,74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATES D2957, AUGUST 19B7 - REVISED APRIL 1993 54AC11008. . . J PACKAGE 74AC11008 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations Minimize High-Speed Switching Noise