54F114 Search Results

Contextual Info: ADVANCE INFORMATION SN 54F114, SN 74F114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COM MON CLEAR, AND COMMON CLOCK D2932, MARCH 1987 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

sn74f114

Contextual Info: SN 54F114, S N 7 4 F1 14 DUAL J K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK D2932, MARCH 19B7 —REVISED JA N U A R Y 1989 54F114 Package Options Include Plastic "S m a ll SN74F114 O utline" Packages, Ceram ic Chip Carriers,

74F161 PC

Abstract: 74F163PC 74f500 74f558 74F164PC 74F548PC 74F138d 74F547PC transistor f630 74F253DC
Contextual Info: F a ir c h ild A d v a n c e d S c h o t t k y T L $ 3. HANDLING PRECAUTIONS FOR SEMICONDUCTOR COMPONENTS The follow ing handling precautions should be observed for oxide isolation, shallow junction processed parts, such as FAST or 100K ECL: 1. All Fairchild devices are shipped in conducting foam or anti­

Contextual Info: 54F114. SN74F114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK D 2 9 3 2 , M AR C H 19 8 7 -R E V IS E D JA N U A R Y 1 9 8 9 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil