1996 Search Results

SN74HC74

Contextual Info: SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS094A - DECEMBER 1982 - REVISED JANUARY 1996 Package Options Include Plastic Small-Outline D , Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

tlc3741

Abstract: resistor network 104g 9 pin
Contextual Info: TLC374, TLC374Q, TLC374Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS118A-NOVEMBER 1983-R EVISED OCTOBER 1996 • Single- or Dual-Supply Operation D, J, N, OR PW PACKAGE TOP VIEW • Wide Range of Supply Voltages 2 V to 18 V u 10UT[ • Very Low Supply Current Drain 0.3 mA Typ

Contextual Info: TL16C550C ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS177B- MARCH 1994 - REVISED MARCH 1996 • Programmable Auto-RTS and Auto-CTS • In Auto-CTS Mode, CTS Controls Transmitter • In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

Contextual Info: SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS034B - DECEMBER 1982 - REVISED JANUARY 1996 • • • • • Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HCOO

F2040

Contextual Info: TRF2040 FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT S L W S 0 2 2 -J U N E 1996 Fractional-N/lnteger-N High-Frequency 0.7-2.2 GHz Synthesizer for Radio Frequency (RF) Channel • PW PACKAGE (TOP VIEW)

Contextual Info: TCM29C23, TCM129C23 VARIABLE-FREQUENCY PCM OR DSP INTERFACE S C T S 0 2 9 A -A U G U S T 1989 -R E V IS E D JULY 1996 • Combined ADC, DAC, and Filters • Extended Variable Frequency Operation - Master Clock Up to 4.096 MHz - Sample Rates Up to 16 kHz - Passband Up to 6 kHz

Contextual Info: TPS9103 POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A - JULY 1996 Charge Pump Provides Negative Gate Bias for Depletion-Mode GaAs Power Amplifiers GATE_BIAS □ = 10 VCC C1c i+ BATTJN BATTJN BATTJN PGP PG GND 2 3 4 5 6 7 8 9 10 135-mli High-Side Switch Controls Supply

DACC

Contextual Info: TLV5621E LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER _ • • • • • S L A S 1 3 8 -APRIL 1996 2.7-V to 5.5-V Single-Supply Operation • Low Power Consumption Three 8-Bit Voltage Output DACs • Half-Buffered Output • Power-Down Mode

SN54LV14

Abstract: 2020CN
Contextual Info: SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS _ S C L S 1 8 7 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-|i Process SN54LV14 . . . J OR W PACKAGE SN74LV14. . . D, DB, OR PW PACKAGE (TOP VIEW) TVplcal V q l p (Output Ground Bounce)

051b

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B - MARCH 1987 - REVISED JULY 1996 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54F13 8 . . . J PACKAGE SN74F138. . . D OR N PACKAGE TOP VIEW u Incorporates Three Enable Inputs to

Contextual Info: SN54LVU04, SN74LVU04 HEX INVERTERS S C L S 1 B 5 B - FEBRUARY 1993 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)

c4885

Contextual Info: TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP S C T S 0 2 1 C - A U G U S T 1 9 8 7 - R E V IS E D J U L Y 1996 Reliable Slllcon-Gate CMOS Technology DW OR N PACKAGE T O P V IE W Low Power Consumption - Operating M o d e . . . 80 mW

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

Contextual Info: SN54HC367, SN74HC367 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS _ SCLS309A - JANUARY 1996 - REVISED JULY 1996 High-Current 3-State Outputs Drive Bus Lines, Buffer Memory Address Registers, or Drive up to 15 LSTTL Loads True Outputs SN54HC367

Contextual Info: SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS174A - MARCH 1984 - REVISED JANUARY 1996 Inputs Are TTL-Voltage Compatible SN54HCT240. . . J OR W PACKAGE SN74HCT240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer

SN54HCT240

Abstract: 8S63
Contextual Info: SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS _ SCLS174A - MARCH 1984 - REVISED JANUARY 1996 • Inputs Are TTL-Voltage Compatible • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • SN54HCT240 . . . J OR W PACKAGE

Contextual Info: SN54HCT125, SN74HCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS069S- NOVEMBER 198« - REVISED MARCH 1996 • ■ I • • Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers I I •

Contextual Info: TLV1VJ1 T IV 1V J1Y SINGLE DIFFERENTIAL COMPARATORS ^ _ SLCS128A - APRIL 1996 - REVISED APRIL 1996 • Low-Voltage and Singie-Supply Operation Vcc = 2 V to 7 V DBV PACKAGE TOP VIEW • Common-Mode Voltage Range Includes Ground

n373

Contextual Info: TCM38C17 QCombo FOUR-CHANNEL QUAD PCM COMBO S L W S 0 40 - J U N E 1996 Single 5-V Supply DGG PACKAGE (TOP VIEW) R B IA S [ Reliable Submicron Sillcon-Gate CMOS Technology Low Power Consumption (per Channel) - Operating Mode. . . 40 mW Typical - Power-Down Mode. . . 1 mW Typical

Contextual Info: TL16PNP100A STANDALONE PLUG-AND-PLAY PnP CONTROLLER SLLS200B - MARCH 1995 - REVISED MARCH 1996 PnP Card Autoconfiguration Sequence Compliant Supports TVvo Logical Devices Decodes 10-Bit I/O Address Location With Programmable 1-, 2-, 4-, 8-, 16-Byte Block

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _SCASS21C- AUGUST 199S - REVISED SEPTEMBER 1996 EPIC Enhanced-Performance Implanted CMOS 1-|im Process SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE

Contextual Info: SN54LV138, SN74LV138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SC LS190P- FEBRUARY 19 9 3 - REVISED JULY 1996 EPIC Enhanced-Performance Implanted CMOS 2-fi Process Typical Vqlp (Output Ground Bounce) < 0.8 V at Vc c , Ta = 25°C SN54LV138. . . J OR W PACKAGE

Contextual Info: TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY S M K S 891C - A U G U S T 1996 - R EVISED O C TO BE R 1997 This data sheet is applicable to TMS418160As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section.

TL751M10

Contextual Info: TL750M, TL751M SERIES LOW-DROPOUT VOLTAGE REGULATORS SLVS021D - JA N U A R Y 1986 - REVISED A U G U S T 1996 • 60-V Load-Dump Protection • Very Low Dropout Voltage, Less Than 0.6 V at 750 nr A • Overvoltage Protection • Internal Thermal Overload Protection