1990 Search Results

Contextual Info: TLE2037, TLE2037A EXCALIBUR LOW -NOISE HIGH-SPEED PRECISION DECOM PENSATED OPERATIONAL AM PLIFIERS D3454, MAY 1990 - REVISED APRIL 1991 available features Outstanding Combination of DC Precision and AC Performance: Gain-Bandwldth Product. . . 80 MHz Typ V

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

i486

Contextual Info: SN74BCT2141 2-WAY 8K x 18 SYNCHRONOUS CACHE DATA RAM D3613. A UG UST 1990 2-Way 8K x 18 Bit Architecture FN PACKAGE TOP VIEW Synchronous Read and Write Access at 50 MHz Clock Frequency Incorporates Burst Counter for Burst-Read (Read-Hit) Cycles or Burst-Write (Line-Fill)

Contextual Info: SN74ALS233B 16x5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253 - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs DW OR N PACKAGE TOP VIEW • 16 Words by 5 Bits OE [ 1 FULL-1 [ 2 • Data Rates From 0 to 40 MHz • Fall-Through Ti me. . . 14 ns Typ

Contextual Info: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ SCAS115- D3456, MARCH 1990-REVISEDAPRIL 1933 Inputs Are TTL-Voltage Compatible Independent Registers A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths

27C020-12

Abstract: 27PC020-12 LS020 A1025 LS020B 2097152-BIT
Contextual Info: TMS27C020 2097152-BIT UV ERASABLE PROGRAMMABLE TMS27PC020 2097152-BIT PROGRAMMABLE READ-ONLY MEMORY SM LS020B - N O V E M B E R 1990 - REVISED JU N E 1995 • Organization . . . 256K x 8 J PACKAGE TOP VIEW • Single 5-V Power Supply • Operationally Compatible With Existing

Contextual Info: AM26LS31C QUADRUPLE DIFFERENTIAL LINE DRIVER _D 2433. JA N U A R Y 19 7 9 -R E V IS E D M AY 1990 Meets EIA Standard RS-422-A D, J, OR N PAC KAG E TOP V IE W Operates From a Single 5-V Supply 1Y [ 2 16 ] V C C 15 ] 4 A 1Z[ ENABLE G [

Contextual Info: SN54ALS1244A, SN74ALS1244A OCTAL BUFFERS AND DRIVERS WITH 3-STATE OUTPUTS SD A S1B 6B-JU LY 1990-R E V IS E D JANUARY 1995 Low-Power Versions of 'ALS244 Series 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading

tip 40c

Contextual Info: TCM1030, TCM1060 DUAL TRANSIENT-VOLTAGE SUPPRESSORS _ Meets or Exceeds Bell Standard LSSGR Requirements 1989-REVISED DECEMBER 1990 D OR P PACKAGE TOP VIEW T IP [ , u vs[ 2 NC[ 3 RING[ 4 Wide, Accurately Controlled, Negative Firing Voltage Range . . . - 5 V to - 65 V

Q7910

Abstract: SN74ALS2232A
Contextual Info: SN74ALS2232A 64 x 8 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY D3091, F E B R U A R Y 1988 - R E V IS E D M A R C H 1990 Independent Asynchronous Inputs and Outputs NT PA C K A G E ITO P VIEW [ DOC D1 C D2C D3C 64 Words by 8 Bits rst Data Rates from 0 to 40 MHz

Contextual Info: SN54BCT2828B, SN74BCT2828B 10-BIT BUS/MOS MEMORY DRIVERS WITH 3-STATE INVERTING OUTPUTS _ D3635, SEPTEMBER 1990 S N 54B C T282B B . . . J T P A C K A G E BiCMOS Design Substantially Reduces S N 7 4B C T 28 2 8B . . . D W O R N T P A C K A G E

74AC11827

Contextual Info: 54AC11827, 74AC11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0155— 0 3 3 7 9 . NOVEMBER 1989— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54AC11827 . . . JT PACKAGE 74AC11827 . . . DW OR NT PACKAGE TOP VIEW

D3440

Contextual Info: TLE2027M, TLE2027AM EXCALIBUR LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIERS D3440, MAY 1990, REVISED OCTOBER 1991 available features Outstanding Combination of DC Precision and AC Performance: Unity-Galn Bandwidth . . . 15 MHz Typ V n_3.3 nV/VHz at f = 10 Hz Typ,

jiA741

Contextual Info: MC3303, MC3403 QUADRUPLE LOW-POWER OPERATIONAL AMPLIFIERS _ SLOS1Q1 - FEBRUARY 1979 - REVISED SEPTEMBER 1990 Wide Range of Supply Voltages Single Supply . . . 3 V to 36 V or Dual Supplies • Class AB Output Stage • True Differential Input Stage

2a117

Contextual Info: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

Contextual Info: TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT D3128.AUG UST1989- HEVISEDFEBRUARY 1990 • Capable o f Running w ith A ll Existing TL16C450 Software N PACKAGE TOP VIEW • A fte r Reset, A ll R egisters Are Identical to the TL16C450 Register Set DOC l U D1C

Contextual Info: SN74ALS229B 16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SPAS09Q - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs • 16 Words by 5 Bits • Data Rates From 0 to 40 MHz • Fall-Through Time. . . 14 ns "typ • 3-State Outputs

26c32c

Abstract: 26C32I
Contextual Info: AM26C32C, AM26C32I QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS104B- D3634, DECEMBER 1990-R EV ISE D DECEMBER 1992 Meets EIA Standards RS-422-A, RS-423-A, and CCITT Recommendation V.11 □, N, OR N S t PACKAGE TOP VIEW Low Power, Ice = 9 rnA Typ 1B[ ±7-V Common-Mode Range With ±200-mV

D425G

Abstract: ACT21 SN74BCT2166
Contextual Info: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs SCHS012-D3513, JUNE 1990-REVISED NOVEMBER 1991 SN74BCT2163, SN74BCT2164 Fast Address to MATCH Delay. 12 ns Max FM PACKAGE CTOP VIEW ’BCT2163 Has Totem-Pole Match Output Q\*~

Contextual Info: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to

Contextual Info: 54AC11853, 74AC 11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS TI0157— D3473, MARCH 1990 54AC11B53 . . . JT PACKAGE 74AC11853 . . . DW OR NT PACKAGE High-Speed Bus Transceivers with Parity Generator/Checker TOP VIEW Parity Error Flag Open-Drain Output • Register for Storage of the Parity Error Flag

Contextual Info: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [