1987 MICRON TECHNOLOGY Search Results

Contextual Info: MX SERIES 1.55-MICRON 2-LAYER METAL SILICON GATE CMOS GATE ARRAYS MATRA DESIGN SEMICDNDUCIDR Advance Information September 1987 FEATURES • Advanced 1.55u 2-layer metal CMOS technology • High perfomance - 1 .5ns delay through 2-input NAN D gate Ta= 25 deg C, VDD = 5V, fanout= 3 + 1OOOum

Contextual Info: * AT&T Preliminary Data Sheet ALA400/401 Linear Array Family Description The ALA400/401 Linear Array Family is fabricated using the complementary bipolar integrated circuit CBIC process that offers the advantages of vertical NPN and vertical PNP transistors. CBIC technology

2500ECL

Abstract: Motorola Bipolar Power Transistor Data Double Die IC 566 function generator HCA62A17 CMOS 4032 1987 Micron Technology Micron NAND bca 1st motorola ECL motorola mca
Contextual Info: BR334/D Rev 3 Motorola Semicustom gives the designer the same process-technology choices available for discrete-logic designs, and the option of Macrocell array or cell-based func­ tions for commercial and military applications. • For very high speeds — state-of-the-art ECL arrays.

pnp 8 transistor array

Abstract: ALA400 transistor BIPOLAR npn 8 transistor array 1000 volt pnp transistor JFET 401 ARRAY resistor DS87-61LBC kss 216 complementary JFET
Contextual Info: AT&T Preliminary Data Sheet ALA400/401 Linear Array Fam ily Description The ALA400/401 Linear Array Family is fabricated using the complementary bipolar integrated circuit CBIC process that offers the advantages of vertical NPN and vertical PNP transistors. CBIC technology

Contextual Info: Integrated Device Technology. Inc C M O S PARALLEL FIR ST-IN/FIRST-O UT FIFO 8K x 9-BIT advance in fo r ^ ion 1017205 FEATURES: DESCRIPTION: • • • • • • • • • • • • • • The IDT7205 is a dual-port memory that utilizes a special FirstIn/First-Out algorithm that loads and empties data on a first-in/firstout basis. The device uses Full and Empty flags to prevent data

nmos transistor 0.35 um

Abstract: P854 "vlsi technology" abstract for intel gelato FEM95 20VOLTS his 06 P856
Contextual Info: Intel’s 0.25 Micron, 2.0Volts Logic Process Technology A. Brand, A. Haranahalli, N. Hsieh, Y.C. Lin, G. Sery, N. Stenton, B.J. Woo California Technology and Manufacturing Group, Intel Corp. S Ahmed, M. Bohr, S. Thompson, S. Yang Portland Technology Development Group, Intel Corp.

Contextual Info: Am29027 Arithmetic Accelerator ADVANCE INFORMATION ¿Z06ZWV DISTINCTIVE CHARACTERISTICS • • • • • • High-speed floating-point accelerator for the Am29000 processor Comprehensive floating-point and integer instruction sets Single-, double-, and mixed-precision operations

austek

Contextual Info: UNITED MICROELECTRONICS U M 8 2 ÍS 2 3QE D =1325052 00 001 72 7 5 3 33-.31 - Cache Controller Features • ■ ■ ■ Controls 32-kB, 4-way r set-associative cache Available in 16-MHz, 20-MHz, and 25-MHz speeds Direct interface to the 80386 Direct interface to industry-standard 8K x 8 SRAMs:

6REV

Contextual Info: ADVANCE -. TE C? x .N-StÜT ü H E MT28F016S2 FLASH MEMORY S m artV oltag e • • • • • • • • • PIN ASSIGNMENT Top View Thirty-two 64KB erase blocks Programmable sector protect Deep Power-Down Mode: lO pA M A X Second Generation Sm artVoltage Technology (SVT-II):

IDT7205

Contextual Info: INTEGRATE» D E V I C E T ? j i| 4Ö5S771 DDDlñOT b | ~ i 4825771 INTEGRATED DEVICE Integrated DevlceTfechnblogy. Inc. 97D 01809 ADVANCE INFORMATION IDT7205 CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO 8 K x 9-BIT T -*/b-35 FEATURES: DESCRIPTION: • • • •

Contextual Info: PRELIMINARY !. A S H M E M O F? V FLASH MEMORY MT28F200B5 ET, MT28F400B5 ET, MT28F800B5 ET Smart 5 Extended Temperature FEATURES PIN ASSIGNMENT Top View • Extended temperature range operation: -40°C to +85°C • Boot block architecture: 16KB/4K-word boot block (protected)

ATMEL AT27c512

Abstract: 27C512 128K ATMEL 515 AT27C512 27c513 27C515-15 27C512 27C512 RESET 27C512-15 atmel 748
Contextual Info: Features * Paged Configurations with Page Reset on Power-Up AT27C512 - Not Paged, 64K x 8 AT27C513 - 4 Pages, 16K X 8 AT27C515 - 2 Pages, 32K x 8 * Low Power CMOS Operation 100 jjlA max. Standby 40 mA max. Active at 5 MHz * Fast Read Access Time - 120ns * Wide Selection of JEDEC Standard Packages incl. OTP

MT28F400B1

Contextual Info: *V K p i i c z R a f s j v O O i B!. i ' * f FLASH MEMORY m a r tV o lt a g e PIN ASSIGNMENT Top View 44-Pln SOP » Seven erase blocks: 16KB/8K-word boot block (protected) Two 8KB /4K-word param eter blocks Four main memory blocks • SmartVoltage Technology (SVT):

upd 1987

Contextual Info: t.fc MT28F200B1 FLASH MEMORY m artV o lt a g e FEATURES PIN ASSIGNMENT Top View • Five erase blocks: 16KB/8K-word boot block (protected) Two 8KB/4K-word param eter blocks Two main memory blocks • SmartVoltage Technology (SVT): 3.3V +0.3V o r 5V ±10% Vcc

ic 4440

Abstract: Delco Marelli bosch M 1.5.4 chrysler ic chrysler vision seagate bosch digital fundamentals triac
Contextual Info:  pre99whi - 1 - May, 19th, 1999 STMicroelectronics MISSION To offer strategic independence to our partners worldwide, as a profitable and viable broad range semiconductor supplier. pre99whi - 2 - May, 19th, 1999 STMicroelectronics : A GLOBAL SEMICONDUCTOR COMPANY

Yamaichi IC51-0644-807 footprint

Abstract: IC51-0562-1514 footprint ssop 0.635 IC51-0562 socket IC51-0644-807 IC51-0804-808 Yamaichi IC51-0804-808 tqfp 56 socket SN700870PM SN700782PCB
Contextual Info: FIFO Memories: Fine-Pitch Surface-Mount Manufacturability First-In, First-Out Technology Tom Jackson Advanced System Logic – Semiconductor Group SCZA003A 1 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor

dc cdi schematic diagram

Abstract: cdi schematic DD139 Newmarket Microsystems cdi schematic diagram Newmarket Transistors DD240 DD193 level shifter from TTL to CMOS bidirectional Newmarket Transistors 275
Contextual Info: ^ 1 ^ 1 CSB8000 SERIES HCMOS Channelless Logic Arrays C A LIFO R N IA DEVICES IN C . PRELIMINARY DATA SHEET November 1987 CSB8000 SERIES FAMILY ORGANIZATION PRODUCT FEATURES • High performance 1.5/tm silicon gate HCMOS technology. Total Pads I/O Pads

F16204

Contextual Info: F1620 16,384 x 4-Bit Static RAM Military Temperature Range January 1987 PRELIMINARY INFORMATION Memory & High Speed Logic Description Connection Diagrams The F1620 is a 65,536-bit fully-static, asynchronous, random access memory organized as 16,384 words by 4-bits per word.

audio echo ic

Abstract: AN-503 cake power audio Echo kb capacitor-array binary-weighted Combo Driver TRANSISTOR D 1978 C1995 TP3054 Why R-C Networks And Which One For Your Converter
Contextual Info: National Semiconductor Application Note 503 Chris Stacey Roy Batruni and Jim Weiser December 1987 IS ASP STILL ALIVE Many circuit designers in the Telecommunications industry may have heard the term ‘‘Digital Signal Processing’’ DSP so many times in recent years that perhaps they now assume that ‘‘Analog Signal Processing’’ (ASP) is a dying art

F1620-35

Abstract: F1620-45 F1620-55 F16204 DMQB
Contextual Info: F1620 16,384 x 4-Bit Static RAM Military Temperature Range FA IR C H IL D A Schlumberger Company January 1987 PRELIMINARY INFORMATION Memory & High Speed Logic Description Connection Diagrams The F1620 is a 65,536-bit fully-static, asynchronous, random access memory organized as 16,384 words by 4-bits per word.

EMI feed-thru

Abstract: Pi filter array design 22mfd emi suppression utilizing
Contextual Info: TECHNICAL INFORMATION PE SERIES CAPACITORS DECOUPLING AND/OR FILTERING by John D. Prymak AVX Corporation Abstract: Decoupling is a means of eliminating or reducing those elements which restrict high speed operations. Filtering is driven by two considerations – emission and susceptance. The noise generated

Contextual Info: LSI LOGIC LCA100K Compacted Array Plus Series 0.7-Micron HCMOS Preliminary The LCA100K Compacted Array Plus series is an HCMOS array-based ASIC product offering ex tremely high performance, combined with very high gate counts. The LCA100K series is manufactured

Contextual Info: PRELIM INARY p i l C R Q ’ i! r\ v. '’ t- f M !. I i ü ü ? \ FLASH MEMORY h L. A b i ' 1 ’ IYIBG x rf i„IE i\,1 0 h V MT28F800B1 FEATURES • Eleven erase blocks: 16KB/8K-word boot block protected Two 8KB/4K-word parameter blocks Eight main memory blocks

vhdl code for 8 bit barrel shifter

Abstract: 16 bit single cycle mips vhdl MOTOROLA DSP56300 architecture pga 132 packaging architectural block diagram of motorola 563xx vhdl code for 16 bit barrel shifter TQFP112 563xx 32 bit single cycle mips vhdl 32 bit barrel shifter vhdl
Contextual Info: Digital Signal Processing Division Introducing Motorola DSP’s 24-bit DSP56300 Architecture and Family The Industry’s Fastest & Most Robust DSP Solution Introduction Date: September 25, 1995 1 Digital Signal Processing Division DSP Core Families 563xx Video Decoding