1987 Search Results

54HC573

Contextual Info: SN54HC573, SN74HC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D26B4. DECEMBER 1982-REVISED SEPTEMBER 1987 • High-Current 3-State Output Drive Bus-Lines Directly or Up to 15 LSTTL Loads • Bus-Structured Pinout Package Options Include Plastic "Small

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

Contextual Info: SN74BCT29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER S C B S 257- SEPTEMBER 1987 - REVISED NOVEMBER 1993 DW OR NT PACKAGE • BICMOS Process With TTL Inputs and Outputs T O P V IE W • State-of-the-Art BICMOS Design Significantly Reduces Standby Current

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

Contextual Info: SN74F378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE S D FS 030B - D2932, M ARCH 1987 - REVISED O CTO B ER 1993 Contains Six D-Type Flip-Flops With Single-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Buffered Common Enable Input

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

Contextual Info: SN54HC563, SN74HC563 OCTAL D TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 • High-Current 3-State Output Drive Bus-Lines Directly or Up to 15 LSTTL Loads S N 5 4 H C 5 6 3 . . . J P AC KAG E S N 7 4 H C 5 6 3 . . . D W OR N P AC KA G E

54HC154

Contextual Info: SN54HC154, SN74HC154 LINE TO 16 LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 • Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs • Performs the Demultiplexing Function by Distributing Data From One Input to Any

F251B

Abstract: DFS06
Contextual Info: SN54F251B, SN74F251B 1-0F-8 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SDFS066A - MARCH 1987 - R EVISED O CTO BER 1993 3-State Versions of SN54F151B and SN74F151B 3-State Outputs Interface Directly With System Bus Performs Parallel-to-Serial Conversion

Contextual Info: SN54F20, SN74F20 DUAL 4-INPUT POSITIVE-NAND GATES D2932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs S N 5 4 F 2 0 . . . J PACKAGE S N 7 4 F 2 0 . . . 0 OR N PACKAGE

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: TIEPAL10016P8-3C HIGH-PERFORMANCE ExCL mP A l CIRCUIT D 30 83. D EC E M B E R 1987 • ECL 100K PAL • High-Performance Operation Propagation Delay . . . 3 ns Max JT PACKAG E TOP VIEW I e e • • ■ - 2 2 0 mA Max • Replacement for 100K ECL Logic

PAL16L8 programming specifications

Abstract: TIBPAL16R4 TIBPAL16L8
Contextual Info: TIBPAL16L8-20M. TIBPAL16R4 20M, TIBPAL16R6 20M, TIBPAL16R8 20M TIBPAL 16L8-15C, TIBPAL16R4 15C, TIBPAL 16R615C, TIBPAL 16R8 15C HIGH-PERFORMANCE IMPACT PAL CIRCUITS FEBRUARY 1984-REVISED DECEMBER 1987 • High-Performance Operation Propagation Delay M Suffix . . . 20 ns Max

sn74f160

Abstract: SN54F160
Contextual Info: SN 54F160A, SN 54F162A, SN 74F160A, SN 74F162A SYNCHRONOUS 4-BIT DECADE COUNTERS D2932, MARCH 1987-REVISED JANUARY 1989 • Internal Look-Ahead for Fast Counting • Carry O utput fo r n-Bit Cascading • Fully Synchronous Operation for Counting • Package Options Include Plastic "Sm all

74F138

Contextual Info: S N 5 4 F13 8 , S N 74 F13 8 3-LINE TO 8-LINE D EC O D ERS/D EM U LTIPLEXERS D2932, MARCH 1987 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems S N 54F138 . . . J PACKAGE SN 74F138 . . . D OR N PACKAGE TOP VIEW AC 1 U ,6 3 vcc

LP319

Abstract: IC 74LS00
Contextual Info: I IP 11Q IP7Q 11 LOW POW ER QUAD D IFFER EN TIA L C OM PARATORS 030 44 , OCTOBER 1987-REVISED MAY 1988 • Ultralow Power Supply Current Drain . . . Typically 6 0 /»A • Low Input Biasing Current . . . 3 nA D, J, OR N PACKAGE (TOP VIEW • Low Input Offset Current . . . ± 0 .5 nA

74as74

Contextual Info: SN74ALS74A, SN74AS74, SN54ALS74A, SN54AS74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D 2M 1, APRIL 1982 - REVISED SEPTEM BER 1987 Package Options Includa Plaatlc "Sm a ll OutHna" Package!, Ceramlc Chip Carrlara. and Standard Plattlc and Caramic 300-mll

SN64HC

Contextual Info: SNS4HCT651, SN54HCT652. SN74HCT651. SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS D2B04, MARCH 19B4-REVISED SEPTEMBER 1987 Inputs are TTL-Voltage Compatible S N 6 4 H C T 6 6 1 , S N 6 4 H C T 6 6 2 . . . J T PACKAGE S N 7 4 H C T 6 6 1 . S N 7 4 H C T 6 6 2 . . . O W OR N T PACKAGE

Contextual Info: SN54HC832, SN74HC832 HEX 2-INPUT OR DRIVERS D 2804, MARCH 1 9 8 4 -R E V IS E D SEPTEM BER 1987 SN 54H C 832 . . . J PACKAGE SN 7 4 H C 8 3 2 . . . D W O R N P A C K A G E High-Current Outputs Can Drive Up to 15 LSTTL Loads TO P V IEW Package Options Include Plastic "Small

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: SN54F30, SN74F30 8-INPUT POSITIVE-NANO GATES D2932, MARCH 1987-R E V ISE D JANUARY 1989 SN 54F30 . . . J PACKAG E SN 74F30 D OR N P A C K A G E Package Options Includa Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mII

SDFS089

Contextual Info: SN74F169 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER SDFS089 - MARCH 1987 - REVISED OCTOBER 1393 Fully Synchronous Operation for Counting and Programming d or n package <TOP v i e w Internal Look-Ahead Circuitry for Fast Counting U /D [ 1 C LK [ 2 Carry Output for N-Bit Cascading

051b

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B - MARCH 1987 - REVISED JULY 1996 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54F13 8 . . . J PACKAGE SN74F138. . . D OR N PACKAGE TOP VIEW u Incorporates Three Enable Inputs to