CY7C1360
Abstract: CY7C1360V25 CY7C1362V25
Contextual Info: V CYPRESS CY7C1360V25 CY7C1362V25 PRELIMINARY 256K x36/512K x 18Synchronous Pipelined SRAM Features • Supports 200-M Hz bus • Fully registered inputs and outputs for pipelined oper ation All synchronous inputs pass through input registers controlled
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CY7C4255
Abstract: CY7C4265 CY7C42X5 only-10
Contextual Info: fax id: 5413 1CY 7C42 65 CY7C4255 CY7C4265 PRELIMINARY 8K/16Kx18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features
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CY7C4255
Abstract: CY7C4265 CY7C42X5 cy7c4255-15ac
Contextual Info: fax id: 5413 1CY 7C42 65 CY7C4255 CY7C4265 8K/16Kx18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide
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CY7C4255
Abstract: CY7C4265 CY7C42X5
Contextual Info: fax id: 5413 1CY 7C42 65 Back CY7C4255 CY7C4265 8K/16Kx18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide
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Contextual Info: LH540215/25 SHARP Data Sheet 512x18/1024 x 18 Synchronous FIFO FEATURES • May be Cascaded for Increased Depth, or Paralleled for Increased Width • Fast Cycle Times: 20/25/35 ns • 16-m A -loL Three-State Outputs • Pin-Compatible Drop-In Replacements for
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idt72215b/25blh540215/25512x18/1024j63428+2smt91009fifo flag read write empty full buffer cascade er
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