16KX8 Search Results

16KX8

Abstract: X76F128 X76F
Contextual Info: X76F128 128K 16Kx8+64x8 Secure FEATURES DESCRIPTION • 64-bit Password Security —Five 64-bit Passwords for Read, Program and Reset • 16384 Byte+64 Byte Password Protected Arrays —Seperate Read Passwords —Seperate Write Passwords —Reset Password

AMD27C128

Abstract: 5962-8766105YC 5962-8766106XA GDIP1-T28 5962-8766102XA QP27C128
Contextual Info: QP27C128 April 7, 2009 QP27C128 – 128 Kilobit 16K x 8 CMOS EPROM General Description The QP27C128 is a 16Kx8 (128-Kbit), UV erasable programmable read-only memory. It operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The QP27C128 meets the

405C

Abstract: 948AL Q100
Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

27128 pin diagram

Abstract: intel EPROM 27128 PROGRAM 27128 INTEL 27128 27128 eprom intel 27128 block diagram 23/INTEL 27128A INTEL 27256 EPROM intel 8051 40 pin INTEL 27128A EPROM
Contextual Info: intéT 27128A ADVANCED 128K 16Kx8 UV ERASABLE PROM • inteligent Programming Algorithm — Fastest EPROM Programming ■ inteligent Programming™ Mode —Automated Programming Operations ■ Compatible with 2764A, 27128, 27256 ■ ± 10% Vcc Tolerance Available

405C

Abstract: 948AL Q100 25128vi
Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

Contextual Info: This X76F128 device has been acquired by IC MICROSYSTEMS from Xicor; Inc. X76F128 128K 16Kx8+64x8 Secure FEATURES DESCRIPTION •64-bit Password Security —Five 64-bit Passwords for Read, Program and Reset •16384 Byte+64 Byte Password Protected Arrays The X76F128 is a Password Access Security Supervisor,

Contextual Info: 128K X76F128 16Kx8+64x8 Secure SerialFlash FEATURES DESCRIPTION • 64-bit Password Security — Five 64-bit Passwords for Read, Program and Reset • 16384 Byte+64 Byte Password Protected Arrays — Seperate Read Passwords — Seperate W rite Passwords — Reset Password

405C

Abstract: 948AL Q100 25128vi CAT25128VP2IGT3D
Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

fzt 571

Contextual Info: /= T SG S-THOMSON * 7 . # . It; L i« « ® M 27128A NMOS 128K 16Kx8 UV EPROM • FAST ACCESS TIME: 200ns ■ EXTENDED TEMPERATURE RANGE ■ SINGLE 5 V SUPPLY VOLTAGE ■ LOW STANDBY CURRENT: 40mA max ■ TTL COMPATIBLE DURING READ and PROGRAM ■ FAST PROGRAMMING ALGORITHM

2x3mm

Abstract: AEC-Q100 EDR-7320 MS-001 25128 CAT25128VI-GT3 cat25128
Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM FEATURES DESCRIPTION „ 10 MHz SPI compatible The CAT25128 is a 128-Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64-byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device

Contextual Info: U 128K X76F128 K 16Kx8+64x8 Secure SerialFlash FEATURES DESCRIPTION • 64-bit Password Security — Five 64-bit Passwords for Read, Program and Reset • 16384 Byte+64 Byte Password Protected Arrays — Seperate Read Passwords — Seperate Write Passwords

X76F128

Abstract: a512-byte
Contextual Info: X76F128 128K 16Kx8+64x8 Secure SerialFlash FEATURES DESCRIPTION • 64-bit Password Security —Five 64-bit Passwords for Read, Program and Reset • 16384 Byte+64 Byte Password Protected Arrays —Seperate Read Passwords —Seperate Write Passwords —Reset Password

CYC199

Abstract: sram cross reference CYPRESS SAMSUNG CROSS REFERENCE W24257AK Cypress CROSS 9042 issi w2425 IS1C64AH idt cross reference
Contextual Info: High Speed SRAM Cross Reference Guide Part No. Density bits Org. Voltage Access Pins Time (ns) (bits) Package W2465AJ 64K 8Kx8 5V 12 28 J:SOJ W24129AJ W24L257AJ,Q 128K 256K 16Kx8 32Kx8 5V 3.3V 12 12, 15 28 28 J:SOJ J:SOJ/Q:STSOP W24257AK,J,Q,S 256K 32Kx8

25128vi

Abstract: 25128LI 25128VE TDFN-8 eeprom CAT25128VE-GT3
Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

25128E

Abstract: TDFN-8 eeprom S28E CAT25128VE-GT3 TDFN8 a5
Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

Contextual Info: X76F128 128K 16Kx8+64x8 Secure DESCRIPTION • 64-bit Password Security —Five 64-bit Passwords for Read, Program and Reset • 16384 Byte+64 Byte Password Protected Arrays —Seperate Read Passwords —Seperate Write Passwords —Reset Password • Programmable Passwords

PAC1000

Abstract: WSI MagicPro II Programmer AP1685
Contextual Info: Programmable Peripheral MAP168 DSP Peripheral with Memory Features First-generation Program mable System Device PSD Program mable Security User-Configurable Peripheral with Memory Protects program code 16Kx8 EPROM PSD integrated software environm ent PC-XT/AT/PS2 platform support

Contextual Info: UK 128K X76F128 16Kx8+64x8 Secure SerialFlash FEATURES DESCRIPTION • 64-bit Password Security — Five 64-bit Passwords for Read, Program and Reset • 16384 Byte+64 Byte Password Protected Arrays — Seperate Read Passwords — Seperate Write Passwords

405C

Abstract: 948AL Q100
Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

IDT7M145S

Abstract: A0LA
Contextual Info: .¿ îy tIJ Ib llS ig l IN T E G R A T E D D E V IC E 3ÔE D • M A 2 S 7 7 1 GOObflST T - H ¿ jijp N „ 16Kx8 fjp d y 1 6 K x 8 ID T 7 M 1 4 5 or 8 K x 8 (ID T 7 M 1 4 4 ) op tion u s e d w ith M A S T E R ID T 7 M 1 3 4 or ID T 7 M 1 3 5 m odu les

Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

25128E

Abstract: CAV25128VE-GT3 CAV25128
Contextual Info: CAV25128 128-Kb SPI Serial CMOS EEPROM Description The CAV25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the

25128E

Abstract: TDFN-8 eeprom S28E
Contextual Info: CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In addition, the