15GBPS Search Results

Contextual Info: MAX24101 15Gbps Octal Linear Equalizer General Description The MAX24101 restores high-frequency signal level at the decision-feedback equalizer DFE receiver for highloss backplane and cable channels. This permits the DFE receiver to meet BER goals. At 15Gbps, the MAX24101

"higig header"

Abstract: higig specification higig protocol overview TN1154 cx4 to sma BCM56802 higig pause frame ir9216 BROADCOM higig2
Contextual Info: LatticeSC/M Broadcom HiGig+ 12 Gbps Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1154 Introduction This technical note describes a physical layer HiGig+ 12 Gbps interoperability test between a LatticeSC/M device and the Broadcom BCM56802 network switch. The test was limited to the physical layer up to XGMII of the 10

ARM11 processor block diagram

Abstract: ARM11 processor NFP-3240
Contextual Info: SiNFP-32xx Flow Processor: Ruggedized Netronome NFP; 133 MHz DDR3 Product Highlights • Source-code compatibility including backwards-compatibility with Intel IXP28XX microengines for customer application migration • High-performance solution with low power consumption for a broad

IXP2800

Abstract: ixp2400 rohs Intel IXA SDK Developers Workbench D-128 intel ixa sdk core components ixa sdk IXP2400 IXP2800 microengine
Contextual Info: product brief Intel IXP2800 Network Processor For OC-192/10 Gbps network edge and core applications Product Highlights • Delivers 10 Gbps packet forwarding and traffic management on a single chip ■ Introduces Hyper Task Chaining processing technology that enables deep packet

88E3082

Abstract: Marvell prestera 88E3083 Prestera 88 Marvell Marvell prestera 98 Marvell PHY register map Marvell prestera-ex MARVELL 88 98MX620
Contextual Info: Marvell Technology Restricted Document Do Not Reproduce Pre-release Draft This is the html version of the file . G o o g l e automatically generates html versions of documents as we crawl the web.

3com superstack

Abstract: Crossbar Switches 1000BASE-X 100BASE-FX 28115 "Spanning Tree"
Contextual Info: Performance Optimized Ethernet Switching Lucent Technologies’ Crossbar Switch Architecture: Performance-Optimized Ethernet Switching Abstract Crossbar switches offer substantial benefits in performance scaling when compared with shared memory and shared bus architecture switches. This is because with a crossbar switch,

20/kd 5810

Abstract: kd 5810
Contextual Info: 3 _sz_ 4 3M HIGH SPEED CARD-EDGE CONNECTOR, SPD08 SERIES FIG. 1 FOR POSITIONS 020, 040, 060, W/O LATCH TYPE SHOWN: S PD 08-020-X X -TR DATE CODE YWWD=DATE OF MANUFACTURE A 06mm ADHESIVE POSITIONS DIMENSIONS

higig2 frame format

Abstract: "higig header" EZchip higig2 higig specification verilog code for spi4.2 to fifo higig pause frame marvell 618 datasheet pt36C 0x00900
Contextual Info: LatticeSCM XAUI to SPI4.2 July 2008 Reference Design RD1033 Introduction The XAUI to SPI4.2 X2S4 Bridge reference design is a cost-effective system solution for bridging SPI4.2 based network processors and 10G/10G+ Ethernet switching devices. On the XAUI side, the X2S4 optionally supports the

CN6880

Abstract: 40GBASE-KR4 CN6880-1200 10GBASE-BX4 40GBASE-KR interlaken network processor Cavium Octeon II octeon octeon plus CAVIUM
Contextual Info: ATCA-9405 AdvancedTCA 40G Packet Processing Blade PRELIMINARY DATA SHEET Ideal for high touch and high throughput packet processing applications to support the latest data-intensive network evolution ƒƒ PICMG compliant single-slot AdvancedTCA® blade with