154JC Search Results

Contextual Info: * 5-BIT 2:1 MUX-LATCH SYNERGY SY10E154 SY100E154 SEMICONDUCTOR FEATURES DESCRIPTION • 750ps max. LEN to output ■ ■ ■ ■ ■ ■ Extended 100E Vee range of -4.2V to -5.5V 700ps max. D to output Differential outputs Asynchronous Master Reset Dual latch-enables

CY37128P160-125AC

Abstract: cpld internal CY3600 CY37128P100-167AC Ultra37128 CY37128P84-125JI
Contextual Info: fax id: 6146 : : M : : IP *: ; M : : Ultra37128 .PRELIMINARY W CYPRESS UltraLogic 128-Macrocell ISR™ CPLD Features High speed f|\/lAX = 167 M Hz • 128 m a cro c ells in eig h t logic blocks — t PD = 6.5 ns • In-S ystem R e p ro g ra m m ab le IS R ™

CY3600

Abstract: tI11J CY37128P84-125JI
Contextual Info: fax id: 6146 ÆÊ PRELIMINARY F T V f S T “ ¡T * &*• risaliiJF ;UI Flmßbö Ultra37128 U ltraLogic 128-Macrocell IS R ™ CPLD H ig h s p e e d Features — • 128 m a c ro c e lls in e ig h t lo g ic b lo c k s f MAX = 167 M H z — t PD = 6.5 ns

l11J

Abstract: CY3600 cpld internal
Contextual Info: fax id: 6147 ÆÊ F T V f S T “ ¡T * &*• risaliiJF ;UI Flmßbö PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — f MAX = 125 M Hz • 128 m a cro c ells in eig h t log ic blocks — t PD = 10 ns • 3 .3 V In-S ystem R e p ro g ra m m ab le IS R ™

84154

Abstract: CY37128P84-125JI
Contextual Info: fax id: 6146 Ultra371 28 UltraLogic 128-Macrocell ISR™ CPLD High speed Feat u res - W x = • 128 m acrocells in eight logic blocks 167MHz — tpo = 6.5 ns • In-System R e p ro g ra m m ab le ISR™ — ts = 3.5 ns — JTAG com plia nt on board p rogram m in g

CY3600

Abstract: 37128VP100
Contextual Info: fax id: 6147 1Ult ra371 28 V PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — fMAX = 125 MHz • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG compliant on board programming

CY37128P84-125JI

Abstract: Ultra37000TM CY3600 37128P100
Contextual Info: fax id: 6146 1Ult ra371 28 PRELIMINARY Ultra37128 UltraLogic 128-Macrocell ISR™ CPLD Features • High speed — fMAX = 167 MHz • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG compliant on board programming — tPD = 6.5 ns