14ELECTRONICS Search Results

Contextual Info: KM736V689/L 64Kx36 Synchronous SRAM 64Kx36-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION - Synchronous Operation. . 2 Stage Pipelined operation with 4 Burst. - On-Chip Address Counter. . Self-Timed Write Cycle. - On-Chip Address and Control Registers.

Contextual Info: KM736V790 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark o.o Initial draft December. 15. 1997 Preliminary 0.1 Change speed symbol 6.0/6.7/7.5/8.5 to 60/67/75/85, Change 7.5 bin to 7.2

Contextual Info: KM732V596A/L 32Kx32 Synchronous SRAM 32Kx32-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. W rite Self-Timed Cycle. On-Chip Address and Control Registers.

Contextual Info: KM718V889 256Kx18 Synchronous SRAM Document Title 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. Historv Draft Date REMARK 0.0 Initial draft May . 15. 1997 Preliminary 0.1 Change 7.5 bin to 7.2 January . 13 . 1998 Preliminary 0.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85

Contextual Info: KM736V847 KM718V947 PRELIMINARY 256Kx36 & 512KX18 Flow-Through N/RAM Document T itle 256Kx36 & 512Kx18-Bit Flow Through N/RAM™ Revision H is t o r y Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. April. 09. 1998 Preliminary Modify from ADV to ADV at tim ing.

Contextual Info: KM736V849 KM718V949 PRELIMINARY 256Kx36 & 512KX18 Pipelined NfRAM Document Title 256Kx36 & 512Kx18-Bit Pipelined NfRAM™ Revision History Rev. No. 0.0 History 1. Initial document. Draft Date Remark June. 09. 1998 Preliminary 0.1 1. Changed DC parameters

Contextual Info: KM736V790 128Kx36 Synchronous SRAM Document Tills 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft December. 15. 1997 Prelim inary 0.1 Change speed symbol 6.0/6.7/7.5/8.5 to 60/67/75/85, Change 7.5 bin to 7.2

Contextual Info: PRELIMINARY 256Kx18 Synchronous SRAM KM718V889 Document Title 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date 0.0 Initial draft M ay . 15. 1997 0.1 Change 7.5 bin to 7.2 January . 13 . 1998 0.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85

KM48S2020A

Abstract: km48s2020at K/A8-A10 050S53 1994 sdram 002G5 D02g DD2054 samsung AND 1994 AND sdram
Contextual Info: PRELIMINARY * KM48S2020A CMOS SDRAM 2M X 8 BIT SYNCHRONOUS DYNAMIC RAM GENERAL DESCRIPTION FEA TU RES - JED EC standard 3.3V power supply. - LVTTL compatible with multiplexed address. - Dual bank / Pulse RAS. - W CBR cycle with address key programs. •Latency Access from column address