149PIN Search Results

PGA149-C-S15D-2

Abstract: 149S8
Contextual Info: 149S8 Metal seal 149pin PGA JEDEC Code – 4.5MAX φ1.0TYP 39.0±0.4 35.56±0.3 2.54TYP 3.8±0.3 φ0.46±0.05 39.0±0.4 Weight g R P N M L K J H G F E D C B A 35.56±0.3 2.54TYP EIAJ Package Code PGA149-C-S15D-2.54 15 14 13 12 11 10 9 8 INDEX AREA 7 6 5 4

149C

Contextual Info: PIN GRID ARRAY PACKAGE 149 PIN CERAMIC PGA-149C-A03 EIAJ code : HPGA149-C-S15D-2 149-pin ceramic PGA Lead pitch 100mil Pin matrix 15 Sealing method Metal seal PGA-149C-A03 149-pin ceramic PGA (PGA-149C-A03) 2.54 ± 0.25 (.100 ± .010) 36.00 (1.417) DIA 0.46 ± 0.05

Contextual Info: PIN GRID ARRAY PACKAGE 149 PIN CERAMIC PGA-149C-A09 EIAJ code : HPGA149-C-S15D-3 Lead pitch 100mil Pin matrix 15 Sealing method Metal seal 149-pin ceramic PGA PGA-149C-A09 149-pin ceramic PGA (PGA-149C-A09) 2.54 ± 0.25 (.100 ± .010) 0.46 +– 0.05 0.08

82389

Abstract: Multibus ii protocol BUS22 B1 intel 82389 Multibus II Bus Interface Controller IEEE-1296 Multibus arbitration protocol multibus II architecture specification multibus multibus ARCHITECTURE
Contextual Info: 82389 Message Passing Coprocessor A Multibus II Bus Interface Controller Datasheet Product Features • ■ Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

BA021

Abstract: MPC32389 IEEE-1296 82389 ba021p 290145 BAD22 176526
Contextual Info: in tj 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

cmos ic 4584

Abstract: transistor on 4584 40E-12 CMOS 4584 raytheon Raytheon cmos Raytheon Company 2000 as "300 gate ttl array" raytheon
Contextual Info: RAYTHEON/ SEMICONDUCTOR HE D I 75ci73tI0 0Q0t.5bl 3 Raytheon Company Semiconductor Division Raytheon CGA70E18 CGA40E12 CGA1ME12 High Density Low Power ECL Gate Array Family Features • Superior performance, lower power, and higher density than existing ECL arrays

149C

Contextual Info: PIN GRID ARRAY PACKAGE FUJITSU SEMICONDUCTOR DATA SHEET 149 PIN CERAMIC PGA-149C-A09 EIAJ code : HPGA149-C-S15D-3 149-pin ceramic PGA Lead pitch 100 mil Pin matrix 15 Sealing method Metal seal PGA-149C-A09 149-pin ceramic PGA (PGA-149C-A09) 2.54 ± 0.25

Contextual Info: PIN GRID ARRAY PACKAGE FUJITSU SEMICONDUCTOR DATA SHEET 149 PIN CERAMIC PGA-149C-A03 EIAJ code : HPGA149-C-S15D-2 149-pin ceramic PGA Lead pitch 100 mil Pin matrix 15 Sealing method Metal seal PGA-149C-A03 149-pin ceramic PGA (PGA-149C-A03) 2.54 ± 0.25

Contextual Info: AT&T Product Announcement ATE-Series Digital Bipolar G ate Arrays AT&T Microelectronics is introducing a new series to the family of existing custom gate arrays. The customized high-speed TTL-ECL gate arrays are designed using Scaled-Fast OxideIsolated Logic SFOXIL bipolar

ty9000

Abstract: TY9000A 1g nand mcp TY9000A000CMGF SD4051 TY9000A000 tc58dyg02f2 nand toshiba ty9000 FBGA149 toshiba mcp
Contextual Info: TY9000A000CMGF TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS TENTATIVE Low Power SDRAM and Nand E2PROM Mixed Multi-Chip Package Lead-Free DESCRIPTION The TY9000A000CMGF is a mixed multi-chip package containing a 536,870,912-bit Low Power Synchronous

MCP 256M nand toshiba

Abstract: TY80009000AMGF toshiba mcp FBGA149 toshiba mcp nand 512M nand mcp nand sdram mcp TOSHIBA M9
Contextual Info: TY80009000AMGF TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS Low Power SDRAM and Nand E2PROM Mixed Multi-Chip Package Lead-Free DESCRIPTION The TY80009000AMGF is a mixed multi-chip package containing a 268,435,456-bit Low Power Synchronous DRAM and a 553,648,128-bit Nand E2PROM. The TY80009000AMGF is available in a 149-pin BGA package

ty9000

Abstract: TY9000A ty9000a400 MCP 256M nand toshiba TY9000A400BMGF 1g nand mcp toshiba mcp 512M nand mcp ty90 MCP 1g nand toshiba
Contextual Info: TY9000A400BMGF TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS Low Power SDRAM and Nand E2PROM Mixed Multi-Chip Package Lead-Free DESCRIPTION The TY9000A400BMGF is a mixed multi-chip package containing a 536,870,912-bit 268,435,456-bit x 2devices

Contextual Info: In te l 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device -Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

Contextual Info: 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

Contextual Info: DATA SHEET ÌÀTCT Bipolar Gate Arrays TE3000 Series Gate Array DESCRIPTION CAD FEATURES The TE3000 high-speed gate array is a member of the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 3000 internal gates and has a total o f 168 inputs,

ET3000

Abstract: ER22T m21g ET-30 R04T ET1500 ECL IC NAND IR1P
Contextual Info: FUJITSU MICROELECTRONICS 31E D 374T7Í35 001MbIO 3 E B FMI February 1990 Edition 1.1 FUJITSU DATA S H E E T ET750, ET1500, ET3000, ET4500 ECL Series Gate Arrays_ D E S C R IP T IO N The Fujitsu ET series gate array family Is a group of high-speed gate arrays with

Multibus ii protocol

Abstract: solna d30 176526 multibus II architecture specification
Contextual Info: V L S I Tech n o lo gy , in c . _ VM82C389 MESSAGE-PASSING COPROCESSOR MULTIBUS II FEATURES DESCRIPTION • Full-function, single-chip interface to Parallel System Bus PSB The VM82C389 Message-Passing Coprocessor (MPC) provides a highintegration interface solution for the

1N3064

Abstract: 1N916 TE1000 TE3000
Contextual Info: DATA SHEET ÌAT&T Bipolar Gate Arrays TE3000 Series Gate Array DESCRIPTION CAD FEATURES The TE3000 high-speed gate array is a member of the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 3000 internal gates and has a total o f 168 inputs,

MCA600ECL

Abstract: 35Z diode
Contextual Info: Order this data sheet by MC10951/D M MOTOROLA SEM ICO NDUCTO RS MC10951 MC10L951 MC100951 P.O. B O X 2 0 9 1 2 • P H O E N IX , A R IZ O N A 8 5 0 3 6 A dvance Info rm atio n 12 X 12 EXPANDABLE MULTIPLIERS The MC10951, 10L951 and 100951 are high-speed 12 x 12 m ul­

a06 transistor

Contextual Info: PIN GRID ARRAY PACKAGE 149 PIN CERAMIC PGA-149C-A06 149-pin ceramic PGA Lead pitch 100mil Pin matrix 15 Sealing method Metal seal PGA-149C-A06 149-pin ceramic PGA (PGA-149C-A06) 2.54 ± 0.25 (.100 ± .010) 36.00 (1.417) DIA 1.27 (.050) DIA TYP (4 PLCS) 35.56 (1.400)

82C389

Contextual Info: V LSI Technology, in c VM82C389 MESSAGE-PASSING COPROCESSOR MULTIBUS II FEATURES DESCRIPTION • Full-function, single-chip interface to Parallel System Bus PSB The VM82C389 Message-Passing Coprocessor (MPC) provides a highintegration interface solution for the

IEEE-1296

Abstract: BA017 BA011 271091 M82389 D1301S Multibus ii protocol 176526 BA022 BAD29
Contextual Info: in te i M82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER M ilita ry Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

ET3004M

Abstract: CS31E 4input nor gate ET-3004M
Contextual Info: FUJITSU MICROELECTRONICS 31E D • 374^7^2 D014b2b 7 ■ F M I cP February 1990 Edition 1.1 - FUJITSU D A TA S H EE T ET2004M, ET2009M, ET3004M ET-M Series Gate Arrays DESCRIPTION The Fujitsu ET-M Series of ECL Gate Arrays are designed to provide both fast ECL

HALF ADDER 74

Abstract: half adder ttl 8 bit half adder 74 mb53030 ECL NAND IMPLEMENTATION HALF ADDER Unbuffered LFP4 LDR3
Contextual Info: * * c P September 1990 Edition 2.0 FUJITSU DATA SH EET MB53xxx FURY uSeries GaAs Gate Arrays The Fujitsu FURY gate array series incorporates Fujitsu’s 0.8-micron GaAs self-aligned gate process to produce a family of devices ideally suited to the highest performance applications. Incorporating very