M-25012 states
Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25
Contextual Info: ^ „ CY7C1360V25 CY7C1362V25 W ^ T Y P R F .S S PREUm NARY CY7C 1364V25 256K X 36/256K x 32/512K x 18 Pipelined SRAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max
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cy7c1360v25cy7c1362v2cy7c1364v2536/256k+732/512k200-mhz166-mhz133-mhz100-mhzm-25012 statescy7c1362v25
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CY7C1360
Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25 intel 80.82
Contextual Info: CY7C1360V25 CY7C1362V25 1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device
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cy7c1360v25cy7c1362v25cy7c1364v2536/256k+732/512k200-mhz166-mhz133-mhz100-mhzcy7c1360intel 80.82
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CY7C1360V25
Abstract: CY7C1362V25 CY7C1364V25
Contextual Info: 329 CY7C1360V25 CY7C1362V25 1364V25 PRELIMINARY 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns for 200-MHz device
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cy7c1360v25cy7c1362v25cy7c1364v2536/256k+532/512k200-mhz166-mhz133-mhz100-mhz
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