12950G Search Results
12950G Price and Stock
| Skyworks Solutions Inc SI5335A-B12950-GMClock Generators & Support Products 4-output, any frequency (< 350 MHz), any output, clock generator (Xtal input) | |||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|   | SI5335A-B12950-GM | 
 | Get Quote | ||||||||
|   | SI5335A-B12950-GM | 1 | 
 | Get Quote | |||||||
| Skyworks Solutions Inc SI5335A-B12950-GMRClock Generators & Support Products 4-output, any frequency (< 350 MHz), any output, clock generator (Xtal input) | |||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|   | SI5335A-B12950-GMR | 
 | Get Quote | ||||||||
|   | SI5335A-B12950-GMR | 1 | 
 | Get Quote | |||||||
12950G Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
| EP610
Abstract: PALCE610 CE610H 
 | Original | H-15/25 PALCE610 15-ns 24-pin 28-pin 25-ns EP610 CE610H | |
| Contextual Info: AMDH COM’L: H-15/25 PALCE610 Family EE CMOS High Performance Programmable Array Logic ?. *.? eoV . . s DISTINCTIVE CHARACTERISTICS • AMD's Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins | OCR Scan | H-15/25 PALCE610 15-ns 25-ns 24-pin 28-pin combinat47 | |
| Pal programming
Abstract: EP610 PALCE610 EP610 ORDERING EP610 "pin compatible" 
 | OCR Scan | H-15/25 PALCE610 15-nstpD 25-ns 24-pin 28-pin 025752b Pal programming EP610 EP610 ORDERING EP610 "pin compatible" | |
| PALCE610H-25PC
Abstract: PALCE610H-15PC 12950G-4 PALCE610H-25 EP610 PALCE610 CE610H 
 | Original | PALCE610H-15PC PALCE610H-25PC H-15/25 PALCE610 28-Pin 16-038-SQ 20-Pin 12950G-4 PALCE610H-25 EP610 CE610H | |
| EP610
Abstract: PALCE610 sr flipflop 
 | Original | H-15/25 PALCE610 15-ns 24-pin 28-pin 25-ns EP610 sr flipflop | |
| Contextual Info: FINAL AMDÌ1 COM’L: H-15/25 PALCE610 Family V A RI T I EE CMOS High Performance Programmable Array Logic AN A M D C O M P A N Y DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or | OCR Scan | H-15/25 PALCE610 15-ns 24-pin 28-pin 25-ns 005-inch | |
| PALCE610H-25
Abstract: EP610 PALCE610 lattice 1996 
 | Original | H-15/25 PALCE610 15-ns 24-pin 28-pin 25-ns PALCE610H-25 EP610 lattice 1996 | |
| Contextual Info: FINAL COM’L: H-15/25 Lattice/Vantis PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Lattice/Vantis Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins | OCR Scan | H-15/25 PALCE610 15-ns 24-pin 28-pin 25-ns | |
| 12950GContextual Info: COM'L: H-15/25 FINAL PALCE610 Family AdvaM Tro EE CMOS High Performance Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • AMD's Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins | OCR Scan | H-15/25 PALCE610 15-ns 25-ns 24-pfn 28-pin 12950G |