128TAP Search Results

Contextual Info: NJU26040-18A DSP with eala / eala Stereo Expander / FIR Filter • ■ General Description The NJU26040-18A is a digital audio signal processor that provides the function eala / eala Rebirth or eala expand speaker + 128tap FIR filter. The NJU26040-18A processes a lot of sound sources, such as DVD, CD,

TIP 317t

Abstract: 317T ISL22317 ISL22317TFRTZ ISL22317UFRTZ ISL22317WFRTZ TB347
Contextual Info: ISL22317 Precision Single Digitally Controlled Potentiometer XDCP Data Sheet May 26, 2009 FN6912.0 Low Noise, Low Power, I2C™ Bus, 128 Taps Features The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The

ADC Key 1 603 rs232

Abstract: ISL26104 isl26102 ISL3152 ADS1232 use for weighing ads1232 weigh scale schematic PR40-Precision-SOI schematic diagram PWM solar charger solar usb charger schematic ECG sensor
Contextual Info: INTERSIL SELECTION GUIDE SIGNAL PATH Real Time Clocks Switches/Multiplexers Interface Digital Potentiometers Data Converters High Speed Op Amps Precision Op Amps Precision Instrumentation Amplifiers Precision Voltage References Power Management  Q3/Q4 2012

AD5247

Abstract: ISL90727 ISL90727UIE627Z-TK ISL90727WIE627Z-TK ISL90728 ISL90728WIE627Z-TK
Contextual Info: ISL90727, ISL90728 Single Volatile 128-Tap XDCP Data Sheet August 2, 2006 Digitally Controlled Potentiometer XDCP Features The Intersil ISL90727 and ISL90728 are digitally controlled potentiometers (XDCP). Each device consists of a resistor array, wiper switches, and a control section. The wiper

verilog code for 64 point fft

Abstract: vhdl code for FFT 32 point verilog code for 256 point fft based on asic vhdl code for FFT based on distributed arithmetic verilog code for FFT 32 point 8255 interface with 8051 xilinx logicore core dds verilog code 16 bit processor fft XILINX vhdl code REED SOLOMON encoder decoder VHDL CODE FOR 8255
Contextual Info: 02 001-014_devsys.fm Page 5 Tuesday, March 14, 2000 10:55 AM IP Solutions: System-Level Designs for FPGAs R February 15, 2000 v3.0 2* Background Designers everywhere are using Xilinx FPGAs to implement system-level functions in demanding applications including communications, high-speed networking, image

verilog code for interpolation filter

Abstract: VHDL code for polyphase decimation filter using D 8 tap fir filter verilog vhdl code for 8-bit signed adder 32 bit adder vhdl code verilog code for parallel fir filter 16 bit Array multiplier code in VERILOG verilog code for decimation filter systolic multiplier and adder vhdl code
Contextual Info: AN639: Inferring Stratix V DSP Blocks for FIR Filtering Applications AN-639-1.0 Application Note This application note describes how to craft your RTL code to control the Quartus II software-inferred configuration of variable precision digital signal processing DSP

DC MOTOR CONTROL THROUGH PWM USING IC 555 48v 1a

Abstract: ISL6730 IRS 4 Channel Integrated Class D Audio Driver IC with PWM Modulator R/MOSFET IRS 630 Datasheet ISL21060
Contextual Info: P WERING INDUSTRIAL General-Purpose Factory Automation, Test and Measurement Systems, Building & Home, Energy Generation, Medical Devices and Programmable Logic Controllers P WERING INDUSTRIAL With industry-leading technology in power data acquisition processes utilize sensors and

7.1 channel assembled home theater circuit diagram

Abstract: digital dts dolby 5.1 ic amplifier circuits 500W subwoofer amplifier circuit diagram amplifier subwoofer 300 D2745 500w sound amplifier circuit diagram D2-71583-LR subwoofer 500w digital FIR Filter using circuit D2-74083-LR
Contextual Info: Intelligent Digital Amplifier and Sound Processor D2-7xx83 The D2-7xx83 family of the DAE-6 Digital Audio Engine™ devices are complete System-on Chip SoC audio processor and Class-D amplifier controllers. Integrated DSP processing and configurable audio processing algorithms provide an

AFE8405

Abstract: AFE8405IZDQ CDMA2000-1X
Contextual Info: AFE8405 14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS212 – OCTOBER 2008 1 Introduction 1.1 FEATURES • • • • • • • • 14-Bit 85-MSPS High-Performance Single ADC At fin = 140 MHz, SNR ≥ 71 dBFS, SFDR ≥ 79 dBc At fin = 70 MHz, SNR ≥ 73 dBFS,

"Digital Potentiometer"

Abstract: linear potentiometer 5128e potentiometer vr MAX1574 MAX1722 MAX4238 MAX5128 MAX5128ELA MAX6817
Contextual Info: 19-3929; Rev 0; 1/06 128-Tap, Nonvolatile, Linear-Taper Digital Potentiometer in 2mm x 2mm µDFN Package The MAX5128 nonvolatile, single, linear-taper, digital potentiometer performs the function of a mechanical potentiometer, but replaces the mechanics with a simple 2-wire digital interface. The MAX5128 performs the

schematic diagram 180v dc motor speed controller

Abstract: schematic diagram 48v dc motor speed controller 300khz 600V mosfet driver IC e bike motor controller CCTV SCHEMATIC camera board e-bike tv lcd Schematic Power Supply ISL2111 ISL24822 pwm e-bike
Contextual Info: Design Tools/Applications 18 2009 P RODUCT SELECTION GUIDE Design Tools Applications Support on the Web . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 iSim Online Design Simulation Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

Contextual Info: RF Agile Transceiver AD9361 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM RX1B_P, RX1B_N AD9361 RX1A_P, RX1A_N ADC RX1C_P, RX1C_N RX2A_P, RX2A_N ADC RX2C_P, RX2C_N RX LO TX_MON1 TX LO TX1A_P, TX1A_N DAC DATA INTERFACE RX2B_P, RX2B_N P0_[D11:D0]/ TX_[D5:D0]

GC5018

Abstract: SLWS169 34166 0X13 GC5018IZDL GC5316 44446
Contextual Info: GC5018 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS169A – MAY 2005 – REVISED NOVEMBER 2005 1 Introduction 1.1 • • • • • FEATURES Four 16-Bit CMOS ADC Input Ports Programmable Closed Loop VGA Control With 6-Bit Outputs for Each ADC Input Port Provide Received Total Wide Band Power

diode code GW 17

Abstract: AFE8406IZDQ b0107 Video sync splitter vga AFE8406 CDMA2000-1X FIFO181 BGA484
Contextual Info: AFE8406 14-BIT, 85 MSPS DUAL ADC, 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS168C – MAY 2005 – REVISED OCTOBER 2008 1 Introduction 1.1 FEATURES • • • • • • • • • 14-Bit 85-MSPS High-Performance Dual ADC Dual ADC Can Be Configured Into Single ADC

D 5036

Abstract: DS3906 MAX5436
Contextual Info: Maxim > Design Support > Technical Documents > Tutorials > A/D and D/A Conversion/Sampling Circuits > APP 5036 Maxim > Design Support > Technical Documents > Tutorials > Digital Potentiometers > APP 5036 Maxim > Design Support > Technical Documents > Tutorials > Sensors > APP 5036

MA2000

Abstract: GC5316
Contextual Info: GC5316 www.ti.com SLWS154A − JANUARY 2004 − REVISED MARCH 2004 HIGHĆDENSITY DIGITAL DOWNCONVERTER AND UPCONVERTER FEATURES D Any DUC Can Sum into Any of Four Output D Optimized for CDMA2000−1X and UMTS D Real/Complex DDC Inputs and DUC Outputs D Programmable AGC on DDC Outputs

Contextual Info: MAX5438 RELIABILITY REPORT FOR MAX5438EUB+ PLASTIC ENCAPSULATED DEVICES January 26, 2011 MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086 Approved by Sokhom Chum Quality Assurance Reliability Engineer Maxim Integrated Products. All rights reserved.

ISL23318

Abstract: FN788 amplifier rf marking code RW
Contextual Info: Single, 128-taps Low Voltage Digitally Controlled Potentiometer XDCP ISL23318 Features The ISL23318 is a volatile, low voltage, low noise, low power, I2C Bus™, 128 Taps, single digitally controlled potentiometer (DCP), which integrates DCP core, wiper switches and control

16 AS 15 HB1

Contextual Info: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 AN9720.2 Authors: John Henkelman and Dave Damerow Introduction [ /Title (AN97 20) /Subject (Calculating Maximum Processing Rates of the PDC (HSP5

MAX6173

Abstract: MAX6174 MAX5436 MAX5774 MAX6143 MAX6160 MAX6175 MAX6176 MAX6177 MAX6220
Contextual Info: Maxim > App Notes > A/D and D/A conversion/sampling circuits Automatic test equipment ATE Measurement circuits Voltage references Keywords: voltage references, voltage reference, DAC reference, three terminal reference, reference accuracy, DAC, digital to analog converter,

sc70 CCF

Contextual Info: ISL90727, ISL90728 Single Volatile 128-Tap XDCP Data Sheet December 15, 2011 Digitally Controlled Potentiometer XDCP™ Features The Intersil ISL90727 and ISL90728 are digitally controlled potentiometers (XDCP™). Each device consists of a resistor array, wiper switches, and a control section. The wiper

Contextual Info: ISL90726 Single Volatile 128-Tap XDCP Data Sheet PRELIMINARY June 29, 2005 Digitally Controlled Potentiometer XDCP Features The Intersil ISL90726 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, and a control section. The wiper position is

Contextual Info: ISL90727 Single Volatile 128-Tap XDCP Data Sheet November 8, 2005 Digitally Controlled Potentiometer XDCP Features The Intersil ISL90727 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, and a control section. The wiper position is

MAX2829

Abstract: MAX6820 mosfet 4456 wifi transceiver 100DB PSRR, linear regulator how to check ic ship DS1669 Digital Pot IC app abstract MAX5481 15MHZ
Contextual Info: Maxim > App Notes > A/D and D/A Conversion/Sampling Circuits Amplifier and Comparator Circuits Analog Switches and Multiplexers Audio Circuits Communications Circuits Digital Potentiometers General Engineering Topics Interface Circuits Measurement Circuits