HSP50214 Search Results

Tuner sharp QPSK

Abstract: 9031 code fir filter Numerically Controlled Oscillator HSP50210 HSP50214 HSP50214VC HSP50214VI
Contextual Info: February 2000 Programmable Downconverter Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts digitized IF data into filtered baseband data which can be

CIC interpolation Filter

Abstract: HSP50214 HSP50214A HSP50214B TB349 cic filter
Contextual Info: Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 TM Technical Brief January 1998 TB349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications Calculating the Output Rate • Output Samples at 6.6 MSPS with Output Bandwidths

tuner 3402

Abstract: HSP50210 HSP50214B HSP50214BVC HSP50214BVI
Contextual Info: HSP50214B Semiconductor Data Sheet February 1999 File Number 4450.2 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The

Contextual Info: HSP50214B S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous • Processing Capable of >100dB SFDR

96330

Contextual Info: HSP50214A S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous

16 AS 15 HB1

Contextual Info: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 AN9720.2 Authors: John Henkelman and Dave Damerow Introduction [ /Title (AN97 20) /Subject (Calculating Maximum Processing Rates of the PDC (HSP5

cic filter

Abstract: decimation filters HSP50214 logic diagram of ic 7432 DC variable power center tap HB2-0 HSP50214A HSP50214B
Contextual Info: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note Introduction January 1999 AN9720.2 BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for

Contextual Info: HSP50214 HARRIS S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts

Contextual Info: HSP50214B Semiconductor Data Sheet January 1999 4450.1 File Number Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The

TMS320C50

Contextual Info: ST-114 Product Sheet The board Is controlled through a Windows interface which allows full access to all HSP50214 registers, and provides controls and displays for FM, FSK, BPSK and QPSK signal demodulation. To speed evaluation, the ST-114 includes a Harris HI5703 10 Bit 40

cic filter for digital down converter

Contextual Info: ¡33 M A fiE S » HSP50214 ADVANCE INFORMATION November 1996 Programmable Downconverter Features Description • Up to 52 MSPS Input The HSP50214 Programmable Downconverter converts digitized IF data into data which can be processed by the standard DSP microprocessor. At least 14 bits of dynamic

cic filter

Abstract: HSP50214 HSP50214A HSP50214B cic filter for digital down converter
Contextual Info: TM Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 Introduction AN9720.2 BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for

HSP50210

Abstract: HSP50214B HSP50214BVI SAMPO intersil application note book CORDIC QAM modulation Tuner sharp QPSK
Contextual Info: HSP50214B TM Data Sheet May 2000 File Number 4450.3 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous

Tuner sharp BPSK

Abstract: 16 bit parallel to serial NMT-900 HSP50214 HSP50214VC HSP50214VI HSP50210 polar modulator 3122 adj
Contextual Info: HSP50214 S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts

cic filter

Abstract: cic filter for digital down converter decimation filters transistor 9720 HSP50214 cic2852 AN9720
Contextual Info: Harris Semiconductor No. AN9720 Digital Signal Processing June 1997 Calculating Maximum Processing Rates of the PDC HSP50214 Authors: John Henkelman and Dave Damerow Introduction cess a lower frequency sampling alias of the IF signal should be considered. If the IF is in the lower portion of the A/D

pdc 7ro

Abstract: FEC15 ix 3394
Contextual Info: HSP50214B Semiconductor D a ta s h e e t F e b ru a ry 1999 F ile N u m b e r 4450.2 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The

TB349

Abstract: HSP50214 Resampler sample rate
Contextual Info: Harris Semiconductor No. TB349 Digital Signal Processing June 1997 Calculating the Maximum Output Sample Rate and Bandwidth of the HSP50214 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications interpolation filters is 35MHz/17 = 2.059MHz 28MHz/17 =

cic filter

Abstract: HSP50214 HSP50214A HSP50214B ASSP29 circuit diagram for FIR filter
Contextual Info: Calculating Maximum Processing Rates of the PDC HSP50214, HSP50214A and HSP50214B Application Note January 1999 AN9720.2 Authors: John Henkelman and Dave Damerow Introduction BAND OF INTEREST Configuring the Programmable Digital Downconverter (PDC) requires selecting clock, decimation and interpolation rates for

832 fm

Contextual Info: fÇj HARRIS HSP50214 S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 52 M S P S F ront-E nd P ro cessin g R ates C L K IN and 35 M S P S B ack-E nd Pro cessin g Rates (P R O C C L K ) C locks M ay Be A s yn ch ro n o u s

TMS320C50 specifications

Abstract: tms320c50 ST 9841 harris CA3338A HI5703 HSP45106 HSP50214 ST-114 FSK bit error rate
Contextual Info: SIGTEK I N C O R P O R A T E D ST-114 Harris HSP50214 Downconverter Evaluation Board The ST-114 is a flexible PC/AT ISA bus evaluation platform for the Harris HSP50214 Programmable Downconverter. Within a matter of minutes after installation in a PC, the ST-114 is up and running. The board simultaneously generates and

HSP50214BVC

Contextual Info: fÇ j H A R R H S P 50214B IS S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214B Programmable Downconverter converts

HSP50210

Abstract: HSP50214B HSP50214BVC HSP50214BVI intersil application note book
Contextual Info: HSP50214B Data Sheet February 1999 File Number 4450.2 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter PDC performs down

HSP50214

Abstract: HSP50214A HSP50214B TB349 cic filter
Contextual Info: Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 Technical Brief January 1998 TB349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications • Output Samples at 6.6 MSPS with Output Bandwidths to

Contextual Info: i ? i? ic Sem iconductor | Calculating the Maximum Output Sample Rate and Bandwidth Specifications of the HSP50214 T e c h n ic a l B n e l J a n u a ry 1998 TB 349.1 Authors: John Henkelman and David Damerow Output Sample Rate and Bandwidth Specifications