125 VA PT DTY Search Results

teradyne z1890

Abstract: Sis 968 ispMACH 4000 development circuit gal amd 22v10 22v10 pal gal programming 22v10 Pal programming 22v10 272-BGA GAL programming PALCE* programming
Contextual Info: L A T T I C E S E M I C O N D U C T Programmable Logic Devices O R “A vision of the ultimate system — Lattice provides the tools and analog, digital, and everything in support necessary to utilize each between, instantly re-programmable.” of these building blocks. The

"XOR Gate"

Abstract: 5000VA 5384VE
Contextual Info: ispLSI 5000V Family Architectural Description December 2001 Introduction The ispLSI 5000V Family of In-System Programmable SuperWIDE High Density Logic Devices offers two generations: ispLSI 5000VE and 5000VA. They are based on Generic Logic Blocks GLBs of 32 registered macrocells

FZ 44 NS

Abstract: 1N3064 3CP51
Contextual Info: MIl-N-3Mie/442A 9 AtwfSt 1983 sirPF ffSEirnre-MIL-M-38510/442 USAF 8 Ma rc h 1979 IQUAL 1h 1 (JA I IHN I IRE QU IREMENTS I I REMOVED I M I LI TA RY SPECIFICATION MICROCIR CU IT S, DIGITAL, SCHOTTKY, TTL, D-TYPE REGISTER, W I TH TH REE-STATE OUTPUT, MO NO L I T H I C SILICON

TDK ZCB2206-11

Abstract: TDK noise FILTER zcb2206 ZCB2206-11 E53-S W267 E53-q voltage unit E53-Q E53-C E53-Q3 E53-V35
Contextual Info:
Process Controller with DeviceNet E5EK-DRT Process Controller Conforming to DeviceNet
Conforms to the DeviceNet and connects to a programmable logic controller without any programming
High performance range of 0.1% FS Pt input: -100.0C to 100.0C

therm-o-disc 59T wiring diagram

Abstract: therm-o-disc 59T wiring diagram 66TM 125 va pt dty 59T4190 therm-o-disc 100 59T4200 CS8323 ignition transformer
Contextual Info: 59T, 66T Series Electric Water Heater Controls Snap-Action Bimetal Discs in Both Controls The 59T and 66T series controls are designed to meet the high electrical capacity requirements of electric water heaters. Both use a temperature sensitive bimetal disc to deliver snap action to the

therm-o-disc 59T wiring diagram

Contextual Info: 59T, 66T Series Electric Water Heater Controls Snap-Action Bimetal Discs in Both Controls The 59T and 66T series controls are designed to meet the high electrical capacity requirements of electric water heaters. Both use a temperature sensitive bimetal disc to deliver snap-action to the

IR detector odti make

Abstract: Theta-JC QFP die down 7181 47 CHB 4U1 by 808 dfx PBS-2 CONNECTOR data sheet IC 7404 pml 017 38A IR receiver data sheet 51ED2
Contextual Info: PM P re lim in a r y In fo rm a tio n D a ta S h e e t • I PM C-960840 IS S U E 3 ^ 1 PM C-Sierra, Inc. # I PM 4388 TOCTL OCTAL T1 FRAMER FEATURES • Integrates eight T1 fra m e rs in a sin g le d evice fo r term inating duplex DS-1 signals. • S upports S F a nd E S F fo rm a t DS-1 signals.

Contextual Info: IDT54/74FCT543 IDT54/74FCT543A IDT54/74FCT543C FAST CMOS OCTAL LATCHED TRANSCEIVER Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • IDT54/74FCT543 equivalent to FAST speed The IDT54/74FCT543/A/C is a non-inverting octal trans­ ceiver built using an advanced dual metal CMOS technology.

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors :JÖi'Np Jdt) PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Common I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space

2574A

Contextual Info: CY54/74FCT2374T CY54/74FCT2574T 8-BIT REGISTERS ^ R T cypress FEATURES • Function and pin compatible with FCT & F logic ■ Power-off disable feature ■ 25£2 output series resistors to reduce transmission line reflection noise ■ Matched Rise and Fall times

Contextual Info: P54/74FCT399T/AT/CT FAST QUAD DUAL-PORT REGISTER FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic ESD protection exceeds 2000V FCT-C speed at 6.1ns max. Com'l FCT-A speed at 7.0ns max. (Com'l) Matched Rise and Fall times Power-off disable feature

Contextual Info: P54/74FCT273T/AT/CT OCTAL D FLIP-FLOP FEATURES • Function, Pinout and Drive Compatible with the FCT and F Logic ■ FCT-C speed at 5.8ns max. Com'l FCT-A speed at 7.2ns max. (Com'l) ■ Reduced (typically = 3.3V) versions of Equivalent FCT functions ■ Edge-rate Control Circuitry for Significantly

PAL16R8 mono

Contextual Info: ADV MICRO 0257526 PLA/PLE/ARRAYS TL. D E § ü 2 5 7 5 2 b 00E70Ö4 96D 2 7 0 8 4 D ADV MI CRO P L A / P L E / A R R A Y S PAL16R8 Family 16 L 8 ,16R8 16 R 6 ,16R4 Ordering Inform ation — Newer Products F eatures/B enefits • Standard 20-pln architectures

PLA 16L8

Abstract: PAL16R8B-4CN Monolithic Memories PAL16R8 TL 2521-2 PALC16R8Q-25 16L8B-2 PAL16R8A-4 16r8a-4 4511 pin configuration 16R6
Contextual Info: ADV MICRO 0257526 PLA/PLE/ARRAYS TL. D E § ü 2 5 7 5 2 b 00E70Ö4 96D 2 7 0 8 4 D ADV MI CRO P L A / P L E / A R R A Y S PAL16R8 Family 16 L 8 ,16R8 16 R 6 ,16R4 Ordering Inform ation — Newer Products F eatures/B enefits • Standard 20-pln architectures

61S11

Contextual Info: fax id: 6016 CY7C331 CYPRESS Asynchronous Registered EPLD Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock in­

4 bit odd parity checker

Abstract: 0539SA
Contextual Info: 906ZUIV Am2906 Quad Two-Input OC Bus Transceiver with Parity DISTINCTIVE CHARACTERISTICS • • • Internal 4-bit odd parity checker/generator. R eceiver has output latch for pipeline operation. R eceiver outputs sink 12 mA. Quad high-speed LSI bus transceiver.

74FCT3574

Contextual Info: IDT54/74FCT3574/A ADVANCE INFORMATION 3.3V CMOS OCTAL D REGISTERS 3-STATE Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 0.5 M ICR O N C M O S Technology • ESD > 2000V per M IL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: CY54/74FCT399T QUAD 2-INPUT REGISTERS ^ /C Y P R E S S FEATURES Function, Pinout and Drive Com patible w ith the FCT and F Logic • Pow er-off disable feature ■ M atched Rise and Fall tim es ■ FCT-C speed at 6.1ns max. Com 'l FCT-A speed at 7.0ns max. (Com 'l)

683XX

Abstract: 68HC11 68HC16 A15F PSD411A1 PSD411A2 psd4xx flip flop T
Contextual Info: Programmable Peripheral PSD413F Family Avance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI’s

Avance Logic

Abstract: Z80 CPU APD Arrays Avance Logic A15F PIN DIAGRAM OF 80186 683XX 68HC11 68HC16 PSD411A1 PSD411A2
Contextual Info: Programmable Peripheral PSD413F Family Avance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI’s

Contextual Info: 806ZUIV/Z06ZUIV Am2907/Am2908 Quad Bus Transceivers with Interface Logic DISTINCTIVE CHARACTERISTICS • • • • Quad high-speed LSI bus-transceiver D-type driver register with open-collector bus driver o utput can sink 100mA at O.BV max. Internal 4-bit odd parity checke r/ge n era tor

Contextual Info: P54/74FCT273T/AT/CT OCTAL D FLIP-FLOP FEATURES Fully Compatible with TTL Input and Output Logic Levels 64 mA Sink Current Com’l , 32 mA (Mil) 15 mA Source Current (Com’l), 12 mA (Mil) CMOS for Low-Power Consumption — Typically 1/3 of FAST Bipolar Logic

Contextual Info: I lnce3rated Device Technology. Inc HIGH-SPEED CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE IDT54AHCT377 FEATURES: DESCRIPTION: • Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes The IDT54AHCT377 is an octal D flip-flop built using advanced

Contextual Info: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Com m on I/O TA G Bits - 2 S eparate I/O Status Bits (VLD and D TY) • Optim ized for 256K B cache and 4G B cacheable space