120S2 Search Results

LM373

Abstract: MC1303L LM566 "direct replacement" transistor BD 540 LYS MFC6030 LM566 equivalent LM3039 SN72558P LM370 SN72741P
Contextual Info: Edge Index by Product Family Here is the new Linear Data Handbook from National. It gives complete specifications for devices useful in building nearly all types of electronic systems, from communica­ tions and consumer-oriented circuits to precision instrumentation and computer designs.

Contextual Info: Preliminary 2P E X 4R XR-T5894 Four-Channel E1 Line Interface 3.3V .the analog plus com pany •- -, X« June 1997-3 FEATURES Compliant with ITU G.703 Pulse Mask Template for 2.048Mbps (E1) Rates Logical Inputs Accept either 3.3V or 5.0V Levels Low CMOS Process

wandel goltermann RFZ

Abstract: RFZ-1
Contextual Info: XRT5894 Four-Channel E1 Line Interface 3.3V or 5.0V May 1998-2 FEATURES □ Compliant with ITU G.703 Pulse Mask Template for 2.048Mbps (E1) Rates □ Four Independent CEPT Transceivers □ Logical Inputs Accept either 3.3V or 5.0V Levels Ultra-Low Power Dissipation

Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ STITUTES A PROPRIETARY DESIGN OF PACKARD ELECTRIC DIVISION AND IS NOT TO BE DUPLICATED OR REPRODUCED WITH OUT AUTHORITY OF PACKARD ELECTRIC DIVISION. REVISED GRAPHICS OF CONNECTOR 128228 DJP DJP 12092405 01NO89 A2 ADDED O.C. SPEC. & REVISED

Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ ST IT U T E S A PROPRIETARY DESIGN OF PACKARD E LE C T R IC DIVISION AND IS NOT TO BE D UPLICATED OR REPRODUCED WITH­ OUT AUTHORITY OF PACKARD E LE C T R IC DIVISION. DATE Q - 890005 8S0004 127024 151188 DR CK DKS DKS

MP480

Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ STITUTES A PROPRIETARY DESIGN OF PACKARD ELECTRIC DIVISION AND IS NOT TO BE DUPLICATED OR REPRODUCED WITH­ OUT AUTHORITY OF PACKARD ELECTRIC DIVISION. DATE SYM 07FES0 01MYS0 01AUS0 DO NOT SCALE REVISION RECORD DR AUTHORITY

mc75173

Abstract: MC75175
Contextual Info: MOTOROLA MC75172B MC75174B SEMICONDUCTOR! TECHNICAL DATA Advance Information Quad EIA-485 Line Drivers with Three-State Outputs QUAD EIA-485 LINE DRIVERS SILICON MONOLITHIC INTEGRATED CIRCUIT The Motorola MC75172B/174B Quad Line drivers are differential high speed

Contextual Info: 1.5-*0.5'-2 PLCS 36.525*0.025 DIA MUST BE SMOOTH FOR O-RING SEAL 8.00 MIN. 21.75*0.25 1.50 R. TYP. DATE SYM 150C87 B REVISION RECORD AUTHORITY REVISED LOCK ARMS AND PINS 4 PLCS. 23MY8E DR CK LT REVISED LOCK ARMS AND CASE DIMENSIONS. 23 JN8S D 02NO86 ADD OVERALL DIMENSIONS.

Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ STITUTES A PROPRIETARY DESIGN OF PACKARD ELECTRIC DIVISION AND IS NOT TO BE DUPLICATED OR REPRODUCED WITH OUT AUTHORITY OF PACKARD ELECTRIC DIVISION. 1SJL88 14FE89 08MR8Ì 14JN8S DO NOT SCALE 0.20 R. MAX. 0.35 MAX. FLAT-

BLH Pressure Transducer specifications

Abstract: BLH Pressure Transducer wiring 2B31J full bridge strain gage pressure sensor BLH DHF 2b31 BLH Pressure Transducer specifications D-HF BLH Pressure
Contextual Info: A N ALO G D E V IC E S FEATURES Low Cost Complete Signal Conditioning Function Low Drift: 0.5fiV/°C max "L" ; Low Noise: 1/iV p-p max Wide Gain Range: 1 to 2000V/V Low Nonlinearity: 0.0025% max ("L") High CMR: 140dB min (60Hz, G = 1000V/V) Input Protected to 130V rmi

samsung p28

Contextual Info: K S O l 19 Multimedia ELECTRONICS VIDEO ENCODER The KS0119/KS0119Q2 combines NTSC encoding with conventional RAM-DAC functions so that digitized video or computer generated graphics can be displayed on either NTSC or PC monitors. There are two data input channels

Contextual Info: CEC 1 '' <901 GEC P L E S S E Y OCTOBER 1991 PRELIMINARY INFORMATION s e m i c o n d u c t o r s DS 2 4 2 '} 3 2 NJ88C33 FREQUENCY SYNTHESISER (r C BUS PROGRAMMABLE WITH CURRENT SOURCE PHASE DETECTOR OUTPUTS (S upersedes S eptem ber 1991 edition) The NJ88C33 is a synthesiser c irc u it fabricated on

6299B

Abstract: 7335a
Contextual Info: UN Doc #; 8384 M I C R O E L E C T R O N I C S The I n f i n i t e P o w e r o f I n n o v a t i o n o d u c t i o n DESCRIPTION The LX8384 is a positive adjustable regulator designed to provide 5A output current with higher efficiency than currently available devices. All internal

12052834

Abstract: 12020137
Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ STITUTES A PROPRIETARY DESIGN OF PACKARD ELECTRIC DIVISION AND IS NOT TO BE DUPLICATED OR REPRODUCED WITH­ OUT AUTHORITY OF PACKARD ELECTRIC DIVISION. DATE SYM AUTHORITY REVISION RECORD 28FE90 VAS PE014387 & RELEASED 08MFH0 Cl REVISED NOTES 1.2.3,4.8 fc 9

Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ STITUTES A PROPRIETARY DESIGN OF PACKARD ELECTRIC DIVISION AND IS NOT TO BE DUPLICATED OR REPRODUCED WITH­ OUT AUTHORITY OF PACKARD ELECTRIC DIVISION. DATE DO NOT SCALE SYM REVISION RECORD DR AUTHORITY CK 07FES0 VAS PE01%78 & RELEASED

Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ STITUTES A PROPRIETARY DESIGN OF PACKARD ELECTRIC DIVISION AND IS NOT TO BE DUPLICATED OR REPRODUCED WITH­ OUT AUTHORITY OF PACKARD ELECTRIC DIVISION. DATE SYM 28MR8S DO NOT S C A LE REVISION RECORD 01AU06 CK 3^0005 DBB DBB

Contextual Info: 7 □0 NOT SCALE DATE D H 15°-2 PLCS PREFERRED, 45° ACCEPTABLE 8 _o pi r s . — COIN EDGES TO ELIMINATE BURRS 7 2 . 8 0 ± 0 . 10 0 .8 0 R. CONSTANT 0 813 +-00.00 24 37 — H M END OF TERMINAL MUST BE FREE OF BURRS - 2 . 0 0 TYP 2 PLCS 0 .6 0 MAX COIN

PE015024

Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ STITUTES A PROPRIETARY DESIGN OF PACKARD ELECTRIC DIVISION AND IS NOT TO BE DUPLICATED OR REPRODUCED WITH OUT AUTHORITY OF PACKARD ELECTRIC DIVISION. DRAWING COMPLETE REVISED REVISED HAS PE015024 & RELEASED REVISED FEM CONN GRAPHICS

Contextual Info: THIS DRAWING AND DESIGN HEREON CON­ STITUTES A PROPRIETARY DESIGN OF PACKARD ELECTRIC DIVISION AND IS NOT TO BE DUPLICATED DR REPRODUCED WITH­ OUT AUTHORITY OF PACKARD ELECTRIC DIVISION. DATE DO NOT SCALE SYM AUTHORITY DR REVISION RECORD 30MY89 26JN8S 17AU8S

8T37

Abstract: 1N3064 400H N8T37 N8T37N
Contextual Info: Signetics 8T37 Bus Receiver Hex Bus Receiver with Hysteresis — Schmitt Trigger Product Specification Logic Products DESCRIPTION The 8T37 is a hex bus receiver with hysteresis organized as two triple receiv­ ers with separate disable lines for each group. Typically the devices may be

Contextual Info: PA05 • PA05A A P E X M IC R O T E C H N O LO G Y C O R P O R A T IO N » A P P L IC A T IO N S H O TLIN E '/ 9 r FEATURES • • • • • • • • HIGH INTERNAL DISSIPATION — 250 WATTS HIGH VOLTAGE, HIGH CURRENT — 100V, 30A HIGH SLEW RATE — 100V/nS

Contextual Info: 128A Series Unit : inch m m 2 -Row Type Sockets • 128A-XXXS2C-LXXX (DIN Reverse Style, Edge Mount Angle Dip) P.C.B. Mounting Holes t = .0 6 3 + .0 0 7 ( 1 .6 ± 0 . 1 9 ) Part Number Number of Contacts A B C D 128A-026S2C-LXXX 26 1.797 (45.64) 1.200 (30.48)

Contextual Info: CS61583 A Cirrus Logic Company Dual T1/E1 Line Interface Features General Description • Dual T1/E1 Line Interface • Low Power Consumption Typically 220mW per Line Interface • Matched Impedance Transmit Drivers The CS61583 is a dual line interface for T1/E1 applica­

Contextual Info: TC40107BP C*MOS DIGITAL INTEGRATED CIRCUIT SILICO N M ONOLITHIC TC40107BP DUAL 2-INPUT NAND BUFFER/DRIVER TC40107BP is a dual 2-input NAND gate, of which output is of open-drain structure by use of N-channel MOS FET. Being capable of driving a large current,