119BALL Search Results
119BALL Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
SOP 8 200MIL
Abstract: serial flash 256Mb fast erase spi TM 1628 IC SOP Micron 512MB NOR FLASH HN29V1G91T-30 HN58C1001FPI-15 M5M51008DFP-70HI 256mb EEPROM Memory CSP-48 TSOP 28 SPI memory Package flash
|
Original |
d-85622rej01c0001-0100zsop 8 200milserial flash 256mb fast erase spi+8 | |
CY7C1361V25
Abstract: CY7C1363V25
|
OCR Scan |
cy7c1361v25cy7c1363v25113-mhz117-mhz+3 | |
CY7C1355CContextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead |
Original |
cy7c1355ccy7c1357ccy7c1355c/cy7c1357c | |
CY7C1382DV33-200BZIContextual Info: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation |
Original |
cy7c1380dv33cy7c1382dv3318-mbitcy7c1380dv33/cy7c1382dv33+1 | |
|
Contextual Info: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need |
Original |
cy7c1352g | |
|
Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD) |
Original |
cy7c1347g | |
IS61LPS102418A
Abstract: IS61LPS25672A IS61LPS51236A IS61VPS102418A IS61VPS25672A IS61VPS51236A IS61LPS51236A-200TQLI 1024Kx18
|
Original |
is61vps25672ais61lps25672ais61vps51236ais61lps51236a+8 | |
N18N1825F1B
Abstract: N18N1833F1B N18N3625F1B N18N3633F1B
|
Original |
n18n1825f1bn18n1833f1bn18n3625f1bn18n3633f1b+6 | |
IS61LPD51218A
Abstract: IS61LPD25636A IS61VPD25636A IS61VPD51218A
|
Original |
is61vpd25636ais61lpd25636ais61vpd51218ais61lpd51218a+5 | |
IS61LPS25632A
Abstract: IS61LPS25636A IS61LPS51218A IS61VPS25636A IS61VPS51218A
|
Original |
is61lps51218ais61lps25636ais61lps25632ais64lps25636a+4 | |
IS64LF12832A-7
Abstract: is64lf12832a LF12836A E0108 IS61LF12836A-6.5B3
|
Original |
lf12832ais64vf12832alf12836avf12836a+9 | |
|
Contextual Info: CY7C1361A CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz Fast OE access times: 3.5 ns and 4.0 ns |
Original |
cy7c1361acy7c1363a36/512k100mhz+1 | |
|
Contextual Info: IS61NLF12836A/IS61NVF12836A IS61NLF25618A/IS61NVF25618A 128K x 36 and 256K x 18 4Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM MAY 2007 FEATURES DESCRIPTION • 100 percent bus utilization The 4 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide |
Original |
is61nlf12836a/is61nvf12836ais61nlf25618a/is61nvf25618a100-pin119-ball+3 | |
|
Contextual Info: IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write |
Original |
is61lps51218ais61lps25636ais61lps25632ais64lps25636a+6 | |
|
|
|||
CY7C1360C-250BGC
Abstract: CY7C1360C CY7C1362C CY7C1360C-166BZI
|
Original |
cy7c1360ccy7c1362c36/512k250-mhz+4 | |
|
Contextual Info: IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI PRELIMINARY INFORMATION JANUARY 2005 FEATURES DESCRIPTION • 100 percent bus utilization The 9 Meg 'NLP/NVP' product family feature high-speed, |
Original |
is61nlp25636a/is61nvp25636ais61nlp51218a/is61nvp51218apk13197lq5m-1982 | |
CY7C1325G
Abstract: CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI
|
Original |
cy7c1325g133-mhz117-mhz100-mhz+8 | |
|
Contextual Info: IS61NLF12836A/IS61NVF12836A IS61NLF25618A/IS61NVF25618A ISSI PRELIMINARY INFORMATION SEPTEMBER 2005 128K x 36 and 256K x 18 4Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEATURES DESCRIPTION • 100 percent bus utilization The 4 Meg 'NLF/NVF' product family feature high-speed, |
Original |
is61nlf12836a/is61nvf12836ais61nlf25618a/is61nvf25618apk13197lq5m-1982 | |
CY7C1327BContextual Info: 327 CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states |
Original |
cy7c1327b100-mhz166-mhz166-mpress | |
CY7C1381B-100AI
Abstract: 381B CY7C1381B CY7C1381B-117AC CY7C1383B
|
Original |
cy7c1381bcy7c1383b36/1mcy7c1381b/cy7c1383b+4 | |
80486 microprocessor block diagram and pin diagram
Abstract: CY7C1338B
|
Original |
cy7c1338b117-mhz100-pin80486 microprocessor block diagram and pin diagram | |
CY7C1354C
Abstract: CY7C1356C
|
Original |
cy7c1354ccy7c1356c36/512k250-mhz | |
CY7C1327G
Abstract: CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI
|
Original |
cy7c1327g250-mhz225-mhz200-mhz+6 | |
GVT71256ZC36B-7.5
Abstract: CY7C1356A-100AC CY7C1356A GVT71512ZC18
|
Original |
cy7c1354a/gvt71256zc36cy7c1356a/gvt71512zc18256kx36/512kx18gvt71256zc36b-7.5+3 | |