1111111111111111I Search Results

Contextual Info: ADVANCE INFORMATION PIO NEER S E M IC O N D U C TO R C O R PO R ATIO N PI6B2402 1111111111111111ii111111111 11 m 1111111111111111111111111 BiCMOS PLL Universal Clock Distribution Chip F eatu res • • • • • • • • • N ear zero propagation delay of ±250 ps (max

P15C16861

Contextual Info: f i PERICOM PI5C16861 PI5C162861 25Q) i i l 1111111 il 1111111111111111i l 1111111111111111111 il 1111il 1111111111i l 1111111111111111 il 111111111111111111111111111 20-Bit, 2-Port Bus Switch Product Features: • Near-zero propagation delay • 5£2 or 25Q switches connect inputs to outputs

Contextual Info: f j j PERI C O M 1111111111111111111111111 II 1111111111 11111111111111111111111111111111111111111 II 111111111111111 1111111111111111II Clock Generation for Pentium II Processor with Direct RAMBUS Memory Features Description • Three copies of CPU Clock @ 133/100 MHz

Contextual Info: P E R ICOM PI5C3383 PI5C32383 25Q 111111 ii 1111111111111111111111111111111111111111111 n 111 5-Bit, 4-Port Bus Exchange Switch Product Features: Product Description: • Near-zero propagation delay

Contextual Info: t}f P E R !C O M Fast CMOS 3.3V 8-Bit Registered Transceiver Product Features • Compatible with LCX and LVT™ families of products • Supports 5V tolerant mixed signal mode operation

Contextual Info: f j j PER I COM 1111111 m PI74LPT16373 iii1111111111111111111 ii 1111111111111111ii111111111111 h 111111111111111111111111111111111111111111111111 Fast CMOS 3.3V 16-Bit Transparent Latch Product Features: Product Description: • C om patible w ith LCX and LV T™ fam ilies o f products

Contextual Info: QUALITY AND RELIABILITY PRODUCT FLOW: SOIC, QSOP, BQSOP, PDIP, PLCC, SOJ, SSOP, TSSOP f j j PERICOM 1 1 1 1 1 1 1 i i i i i 1 1 1 1 1 1 1 1 1 1 1 h i i 1 1 1 1 1 1 1 1 m 111 1111 1111 1111111111111111i i 1111111111111111i i 1 1 n 1 1 1 1 i i 1 1 1 1

LM311

Abstract: ic lm311 circuit diagram LM311 application notes SLCS007A LM311DBLE LM311T LM111 fk package
Contextual Info: LM111, LM211, LM311, LM311Y DIFFERENTIAL COMPARATORS WITH STROBES SLCS007A-SEPTEMBER 1 9 7 3 - REVISED FEBRUARY 1992 LM111 . . . J PACKAGE Fast Response Times TOP VIEW Strobe Capability Maximum Input Bias C u rre n t. . . 300 nA NC[ EMIT O U T [ IN + [ IN -[

AL437

Abstract: L97c L235C L103T L41C L140C L94C l165c L239C L43C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

L130C

Abstract: L74c l31c l97c l65c A311TC l146c l48c L202C L235C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC May 2009 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

12sp7

Abstract: radar tube Scans-0017290
Contextual Info: 12SP7 OSCILLOGRAPH TUBE Magnetic Focus Magnetic Deflection Long-Persistence Screen 54° Deflection Angle 12-9/16" Max. Diameter 19-1/8" Max. Length R C A - I2 S P 7 is a 1 2 -in c h , d i r e c t l y viewed c a t h o d e - r a y t u b e o f t h e m a g n e t i c - f o c u s and

Contextual Info: DRAM MODULES KMM5364100H/HG 4M X 36 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • Performance range: tcAC tRC 15ns 110ns KMM5364100H-7 70ns 20ns 130ns KMM5364100H-8 80ns 20ns 150ns The KMM5364100H is a S ingle In-line M em ory M odule w ith edge connections and is intended fo r m ounting into

L47C

Abstract: L146C L135 l54c L62C L97C verilog code of prbs pattern generator L71C L235C L43C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC February 2005 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

S7350

Abstract: TPS73010 TPS7301 TPS7301Q TPS7333 TPS7333Q TPS7348 TPS7348Q TPS7350 TPS7350Q
Contextual Info: TPS7301Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION SLVS124A - JUNE 1995 - REVISED SEPTEMBER 1995 D PACKAGE TOP VIEW Available in 3.3-V, 4.85-V, and 5-V Fixed-Output and Adjustable Versions Integrated Precision Supply-Vottage

L43C

Abstract: L130C l44c L239C l220c L235C L97c L62C L81C l31c
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC October 2007 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

16pin ic 502

Contextual Info: f j j PER ICOM PI5A381A/383A/385A 1111111111111111111 ii 1111111111111111111111111111 Precision Wide Bandwidth Analog Switches Features Description • Single-Supply Operation +2V to +6V