10GEC Search Results

MB86C69RBC

Abstract: 10G CDR RDK-10G-SFP Gennum SFP SFP layout design TOSA 850 10G gennum cdr fujitsu SFP optical module SFP module SFP ACTIVE COPPER CABLE
Contextual Info: Reducing Power and Costs of 10G Solutions In Data Centers Fueled by data-center performance demands and declining price per port, the 10GbE switch market is poised for rapid growth in the next few years. Gennum and Fujitsu have combined forces to develop 10GbE technology that helps reduce both cost and

Thermonics T-2500

Abstract: thermostream EYE DIAGRAM thermonics HPE3630A ORSO42G5 ORSO82G5 ORT42G5 ORT82G5 10GEC
Contextual Info: ORTx2G5, ORSOx2G5 and ORSPI4 High-Speed Backplane Measurements July 2004 Technical Note TN1027 Introduction The Lattice ORT82G5 and ORSO82G5 FPSC devices contain two Quad-SERDES blocks. The Lattice ORT42G5, ORSO42G5 and ORSPI4 FPSC devices contain one Quad-SERDES block. Each SERDES SERializer/DESerializer provides a serial high-speed backplane transceiver interface, operational at data rates up to 3.7 Gbit/s for the

QorIQ Debug and Performance Monitoring

Abstract: mesa Toshiba MeP secure toshiba mep architecture
Contextual Info: P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual Document Number: P3041RM Rev 3, 6/2013 P3041 QorIQ Integrated Multicore Communication Processor Family Reference Manual, Rev. 3, 6/2013 2 Freescale Semiconductor, Inc. Contents

Contextual Info: Freescale Semiconductor Data Sheet: Technical Data P4040 QorIQ Integrated Processor Hardware Specifications The P4040 QorIQ integrated communication processor combines four Power Architecture processor cores with high-performance data path acceleration logic and network

Contextual Info: P4080 QorIQ Integrated Processor Hardware Specifications Datasheet The P4080 QorIQ integrated communication processor combines eight Power Architecture processor cores with high performance data path acceleration logic and network and peripheral bus interfaces required for power intensive

1156 pin FCBGA

Abstract: 400GB MB8AA3020 cs.212435
Contextual Info: 10GbE Breakthroughs in Bringing Industry’s First MicroTCA Solutions to Market CorEdge Networks was the first standards-based telecom platform maker to develop and demonstrate a commercial microTCA application, the mTCA Carrier Hub MCH , a breakthrough achieved in collaboration with its silicon provider,

QorIQ P4080 reference manual

Abstract: P4080EC P4080 QorIQ Integrated Processor dhrystone p4080 Data Path Acceleration Architecture mdm fuse P4080PSE1MMB P4080-1295 QorIQ Debug and Performance Monitoring e500mc
Contextual Info: Freescale Semiconductor Data Sheet: Technical Data P4080 QorIQ Integrated Processor Hardware Specifications The P4080 QorIQ integrated communication processor combines eight Power Architecture processor cores with high performance data path acceleration logic and network

QorIQ P4040 reference manual

Abstract: TX-6-G QorIQ P4080 reference manual flotherm MODEL e500mc P4080 PME P4040EC Data Path Acceleration Architecture freescale P4040 P4080 PCI-E
Contextual Info: Freescale Semiconductor Data Sheet: Technical Data P4040 QorIQ Integrated Processor Hardware Specifications The P4040 QorIQ integrated communication processor combines four Power Architecture processor cores with high-performance data path acceleration logic and network

Thermonics T-2500

Abstract: T2500E T-2500E picosecond thermostream T2500 1E12 TN1084 2500E signal path designer 105
Contextual Info: LatticeSC High-Speed Backplane Measurements June 2006 Technical Note TN1118 Introduction The LatticeSC device contains multiple SerDes blocks arranged as quads. Each SerDes SERializer/DESerializer provides a serial high speed backplane transceiver interface and is capable of 3.8 GB/s performance.

SY 351/6

Abstract: HP8656B service manual PWB 826 service manual PS 224 CITS25 DXSN2112 pj 939 PS-224 2 X 2 DUAL CROSSPOINT SWITCH amcc 10G palce programming algorithm
Contextual Info: SERDES Handbook April 2003 Dear Valued Customer, Lattice Semiconductor is pleased to provide you this second edition of our SERDES Handbook. Since offering the initial version last year, we have introduced several new products based on our superior sysHSI technology:

TP04100A-1

Abstract: HPE3610A thermostream ps224 TP0410 HPE3630A Bit-Error HP6213A HPE3648A ORT42G5
Contextual Info: ORT42G5 and ORT82G5 High-Speed Backplane Measurements April 2003 Technical Note TN1027 Introduction The Lattice ORT82G5 FPSC device contains two Quad-SERDES blocks. The Lattice ORT42G5 FPSC device contains one Quad-SERDES block. Each SERDES SERializer/DESerializer provides a serial high-speed backplane

QorIQ P4080 reference manual

Contextual Info: Freescale Semiconductor Data Sheet: Technical Data Document Number: P4080EC Rev. 4, 04/2013 P4080/P4081 QorIQ Integrated Processor Hardware Specifications The P4080/P4081 QorIQ integrated communication processor combines eight Power Architecture processor

QorIQ P4080 reference manual

Abstract: P4080NXE1MMB P4080NSE1MMB P4080 QorIQ Integrated Processor P4080N P4080 QorIQ Integrated Multicore Communication P4080NXN1MMB P4080EC QorIQ P4040 reference manual QorIQ dhrystone
Contextual Info: Freescale Semiconductor Data Sheet: Technical Data P4080 QorIQ Integrated Processor Hardware Specifications The P4080 QorIQ integrated communication processor combines eight Power Architecture processor cores with high-performance data path acceleration logic and network

SFP LVDS altera

Abstract: DK-VIDEO-2SGX90N altera jtag ethernet SFP altera Altera 6G FPGA Dev Kit Stratix II GX FPGA Development Board Reference altera cyclone 3 fpga altera cyclone iv JTAG CONNECTOR cyclone iii fpga DK-PCIE-2SGX90N
Contextual Info: Stratix II GX Transceivers with Integrity High-Speed Serial I/O Workshops Q4, 2006 and Q1, 2007 Version 02/2007 2007 Altera Corporation—Confidential Agenda „ „ Stratix II GX overview Complete solution − Transceiver building blocks − Hard IP and IP cores