1024CYCLES Search Results
1024CYCLES Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
MSC2323258DContextual Info: This version: Mar. 3. 1999 Semiconductor MSC2323258D-xxBS4/DS4 2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSC2323258D-xxBS4/DS4 is a fully decoded, 2,097,152-word x 32-bit CMOS dynamic random access memory module composed of four 16Mb DRAMs in SOJ packages mounted with eight decoupling capacitors on a |
Original |
msc2323258d-xxbs4/ds4152-word32-bit72-pin+1 | |
MSC23B236DContextual Info: This version: Mar. 3. 1999 Semiconductor MSC23B236D-xxBS8/DS8 2,097,152-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The MSC23B236D-xxBS8/DS8 is a fully decoded, 2,097,152-word x 36-bit CMOS dynamic random access memory module composed of four 16Mb DRAMs in SOJ packages and four 2Mb DRAMs in SOJ packages mounted with |
Original |
msc23b236d-xxbs8/ds8152-word36-bit72-pin+1 | |
|
Contextual Info: HM5118160BI Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-580A Z Rev. 1.0 May. 20, 1996 Description T he H itachi H M 5118160B I is a C M O S dynam ic R A M organized as 1,048,576-w ord x 16-bit. It em ploys the m ost advanced C M O S technology fo r high perform ance and low pow er. T he H M 5118160B I offers |
OCR Scan |
hm5118160bi1048576-word16-bitade-203-580a+4 | |
|
Contextual Info: - PRELIMINARY - February 1996 Edition 1.0 FUJITSU P R O D U C T PR O F IL E S H E E T MB81V4405C-60/-70 CMOS 1 M X 4 BIT HYPER PAGE MODE DRAM CMOS 1,048,576 x 4 bit Hyper Page Mode Dynamic RAM The Fujitsu MB81V4405C is a fully decoded CMOS Dynamic RAM DRAM that contains 4,194,304 |
OCR Scan |
mb81v4405c-60/-70mb81v4405c024-bitsmb81v4405c-60+4 | |
|
Contextual Info: HY51V S 16163HG/HGL 1M x 16Bit EDO DRAM PRELIMINARY DESCRIPTION The HY51V(S)16163HG/HGL is the new generation dynamic RAM organized 1,048,576 words x 16bit. HY51V(S)16163HG/HGL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The HY51V(S)16163HG/HGL offers Extended Data Out PageMode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)16163HG/HGL to be |
Original |
hy51v16163hg/hgl16bit | |
|
Contextual Info: HM5118160BI Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-580A Z Rev. 1.0 May. 20, 1996 Description The Hitachi HM5118160BI is a CMOS dynamic RAM organized as 1,048,576-word x 16-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5118160BI offers |
OCR Scan |
hm5118160bi1048576-word16-bitade-203-580a+3 | |
MSC23140D
Abstract: DS1067
|
Original |
msc23140d-xxbs10/ds10576-word40-bit72pin+3 | |
|
Contextual Info: K7R323684C K7R321884C K7R320984C Preliminary TM 1Mx36, 2Mx18 & 4Mx9 QDR II b4 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. |
Original |
k7r323684ck7r321884ck7r320984c1mx36+1 | |
JTAG 10P
Abstract: K7R641882M-FC25 K7R640982M-FC25 K7R643682M-FC20
|
Original |
k7r643682mk7r641882mk7r640982m2mx36+7 | |
|
Contextual Info: K7I323684C K7I321884C Preliminary 1Mx36 & 2Mx18 DDRII CIO b4 SRAM 36Mb DDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, |
Original |
k7i323684ck7i321884c1mx362mx18+1 | |
|
Contextual Info: K7J643682M K7J641882M Preliminary 2Mx36 & 4Mx18 DDR II SIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition |
Original |
k7j643682mk7j641882m2mx364mx18+2 | |
|
Contextual Info: Preliminary K7I643682M K7I641882M 2Mx36 & 4Mx18 DDRII CIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition |
Original |
k7i643682mk7i641882m2mx36-bit4mx18-bit+2 | |
a10u
Abstract: B724e
|
OCR Scan |
msm514101b/bl304-word1024cycles/16ms128ms+2 | |
|
Contextual Info: K M 4 4 C 1OOOD J CMOS DRAM ELECTRONICS 1 M x 4 B i t CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 1,048,576 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5.0V or +3.3V , access |
OCR Scan |
16mx4512kx8km44c1000dj003414b | |
|
|
|||
|
Contextual Info: K M4 1 V 4 0 0 0 D J CMOS DRAM ELECTRONICS 4 M x 1 Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 4,194,304 x 1 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5.0V or +3.3V , access |
OCR Scan |
km41v4000djb414e7tb414e003410b | |
|
Contextual Info: KM44V1000DJ CMOS D R A M ELECTRONICS 1 M x 4 B i t CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 1,048,576 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5.0V or +3.3V , access |
OCR Scan |
km44v1000dj16mx4512kx8gd3474+2 | |
|
Contextual Info: KM41C4000C, KM41V4000C CMOS DRAM 4M x 1 Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 4,194,304 x 1 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5.0V or +3.3V , access |
OCR Scan |
km41c4000ckm41v4000c1024cycles00231fc | |
|
Contextual Info: KM44C1000D, KM44V1000D CMOS DRAM 1M x 4Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 1,048,576 x 41 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5V or +3.3V , access time (-5, -6 or -7), power consumption(Normal or Low power), a d |
OCR Scan |
km44c1000dkm44v1000d1024cycles0g37gflc | |
MSC23137DContextual Info: This version: Feb. 23. 1999 Semiconductor MSC23137D-xxBS9/DS9 1,048,576-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The MSC23137D-xxBS9/DS9 is a fully decoded, 1,048,576-word x 36-bit CMOS dynamic random access memory module composed of nine 4Mb DRAMs in SOJ packages mounted with nine decoupling capacitors on a 72-pin glass |
Original |
msc23137d-xxbs9/ds9576-word36-bit72-pin+1 | |
MSC23V26418TD
Abstract: MSC23V26418TD-50BS8 MSC23V26418TD-60BS8 MSC23V26418TD-70BS8
|
Original |
msc23v26418td-xxbs8152-word64-bit1mx16+5 | |
a6eeContextual Info: KM41C4002C CMOS DRAM 4M x 1 Bit CMOS Dynamic RAM with Static Column Mode DESCRIPTION This is a family of 4,194,304 x 1 bit Static Column Mode CMOS DRAMs. Static Column Mode offers high speed random or sequential access of memory cells within the same row. Access time -5, -6, -7 or -8 and |
OCR Scan |
km41c4002ca6ee | |
|
Contextual Info: SGRAM MODULE KMM965G512BQ P N / KMM966G512BQ(P)N 4MB SGRAM MODULE (512Kx64 SODIMM based on 256Kx32 SGRAM) Unbuffered SGRAM Graphics 64-bit Non-ECC/Parity 144-pin SODIMM Revision 2.5 July 1998 Rev. 2.5 (July. 1998) ELECTRONICS SGRAM MODULE KMM965G512BQ(P)N / KMM966G512BQ(P)N |
OCR Scan |
kmm965g512bqkmm966g512bq512kx64256kx32+4 | |
|
Contextual Info: KMM5361000 DRAM MODULES 1 M X 3 6 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • Performance range: The Samsung K M M 5361000 is a 1M bits X 36 Dynamic RAM high density memory module. The Samsung KM M 5361000 consist of eight CMOS 1M X 4 bit DRAMs |
OCR Scan |
kmm536100020-pin72-pin100ns+1 | |
HM5118160B
Abstract: HM5118160BJ-6 HM5118160BJ-7 HM5118160BJ-8 HM5118160BLJ-6 HM5118160BLJ-7 HM5118160BLJ-8 HM5118160BTT-6 HM5118160BTT-7
|
Original |
hm5118160b1048576-word16-bitade-203-476+11 | |