100E1 Search Results

E160

Abstract: SY100E160 SY10E160 SY10E160JC
Contextual Info: 12-BIT PARITY GENERATOR/CHECKER DESCRIPTION FEATURES • Provides odd-HIGH parity of 12 inputs ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E160 are high-speed, 12-bit parity generator/checkers with differential outputs, for use in new, high-performance ECL systems. The output Q takes

E212 transistor

Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, 100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

marking CODE D2B

Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, 100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

MC100E116

Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
Contextual Info: MC10E116, 100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.

E160

Abstract: E193 MC10193 SY100E193 SY10E193
Contextual Info: Micrel, Inc. SY10E193 100E193 SY10E193 ERROR DETECTION/ CORRECTION CIRCUIT FEATURES 100E193 DESCRIPTION • Hamming code generation ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E193 are error detection and correction EDAC circuits designed for use in new, high- performance

MC100E171

Abstract: MC10E171 MC10E171FN
Contextual Info: MC10E171, 100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MC100E151

Abstract: MC10E151 MC10E151FN
Contextual Info: MC10E151, 100E151 5V ECL 6-Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous

MC100E150

Abstract: MC10E150 MC10E150FN
Contextual Info: MC10E150, 100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the

E112

Abstract: E212 MC100E112 MC10E112 E212 transistor
Contextual Info: MC10E112, 100E112 5V ECL Quad Driver Description The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

MC100E163

Abstract: MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2
Contextual Info: MC10E163, 100E163 5VĄECL 2ĆBit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 – A7, B0 – B7) is propagated to the output.

MC100E154

Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
Contextual Info: MC10E154, 100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on

E116

Abstract: SK10E116PJ SK10E116PJT LM 380 FUNCTIONAL BLOCK AN-1002
Contextual Info: SK10/100E116 Quint Differential Line Receiver HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100E116 is a quint differential line receiver designed for use in new, high-performance ECL systems. • • • • • • • • The receiver design features clamp circuitry to cause a

E166

Abstract: SY100E166 SY10E166 SY10E166JC
Contextual Info: 9-BIT MAGNITUDE COMPARATOR FEATURES SY10E166 100E166 DESCRIPTION • 1100ps max. Propagation Delay A = B ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E166 are 9-bit magnitude comparators designed for use in new, high-performance ECL systems.

MC100E157

Abstract: MC100E157FN MC100E157FNR2 MC10E157 MC10E157FN MC10E157FNR2
Contextual Info: MC10E157, 100E157 5VĄECL Quad 2:1 Multiplexer The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.

pdc 140

Abstract: DL140 E195 MC100E195 MC10E195
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

motorola D-latch

Abstract: MC100E150 DL140 MC10E150
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6ĆBit D Latch MC10E150 100E150 The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A

DL140

Abstract: E195 MC100E195 MC10E195
Contextual Info: MOTOROLA Order this document by MC10E195/D SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

Motorola, Inc. identical in pinout to

Abstract: DL140 MC100E171 MC10E171
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 Multiplexer MC10E171 100E171 The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the

Contextual Info: Order this document by MC10E136/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6-Bit U niversal Up/Down Counter M C 10E136 M C 100E136 • 550 MHz Count Frequency • • • • Fully Synchronous Up and Down Counting Internal 75 kQ Input Pulldown Resistors Look-Ahead-Carry Input and Output

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 M 100E195 Program m able Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay ot a differential ECL input transition.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6-Bit Universal Up/Down Counter M C10E136 M 100E136 The MC1OE/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cacading

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9 -B it S h ift R e g is te r M C 10E142 M C 100E142 The M C 10E/100E142 is a 9-bit shift register, designed with byte-parity a p p lic a tio n s in m ind. T h e E142 p e rfo rm s s e ria l/p a ra lle l in and serial/parallel out, shifting in one direction. The nine inputs DO - D8

LC313

Contextual Info: MOTOROLA SEM ICONDUCTO R TECHNICAL DATA 6-Bit D Latch M C10E150 M 100E150 The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 10E 163 M C 100E163 • 850 p s M a x. D to O u tp u t • D iffe re n tia l O u tp u ts • E x te n d e d 100E V g g R ange o f - 4 . 2 V to - 5 . 4 6 V • 75 k i l In p u t P u lld o w n R esisto rs T h e M C 10E/100E163 c o n ta in s tw o 8:1 m u ltip le x e rs w ith d iffe re n tia l o u tp u ts a nd