1004155 Search Results

Contextual Info: HMC121G8 MICROWAVE CORPORATION G a A s M M IC S M T V O L T A G E -V A R IA B L E A T T E N U A T O R D C - 8 G H z FEBRUARY 1998 Features WIDE BANDWIDTH: General Description D C - 8 GHZ The HMC121G8 is an absorptive voltage variable attenuator provided in a surface-

Contextual Info: JT2F D evice 6 Mbit/s JT2 Framer TXC-03702B DATA SHEET Product Preview DESCRIPTION 11 = The JT2 Framer JT2F is a CMOS VLSI device that provides the functions needed to frame a wideband payload to ITU G.704 and the NTT-specified 6312 kbit/s frame format for ATM operation. The JT2F interfaces to

Contextual Info: E2/E3F Device 8-, 34-Mbit/s Framer TXC-03701B DATA SHEET FEATURES DESCRIPTION • Framer for ITU-TSS Recommendations: - G.742 8448 kbit/s - G.745 (8448 kbit/s) - G.751 (34368 kbit/s) - G.753 (34368 kbit/s) The E2/E3 Framer (E2/E3F) is a CMOS VLSI device

Contextual Info: SARA Chipset Technical Manual Segmentation SARA Hardware Description Chapter 3. Hardware Description 3.1 Segmentation SARA Hardware Description 3.1.1 Segmentation SARA Internal Block Description Figure 3-1 shows a block diagram of the Segmentation SARA chip.

M39012/30-0503

Abstract: QPL-39012 M39012 M39012/26-0225 1101-004-A00E-1 M39012/28-0503 M39012-16-0220 m39012/55b3022 KD-59 KC-59
Contextual Info: DLA Land and Maritime - VQ Supplemental Information Sheet for Electronic QPL-39012 Specification Details: Date: 9/21/2010 Specification: MIL-PRF-39012 Title: Connectors, Coaxial, Radio Frequency Federal Supply Class FSC : 5935 Conventional: Yes Specification contains quality assurance program: No

Contextual Info: GaAs MMIC High-lsolation SPDT Switch HITTITE MICROWAVE CORPORATION HMC132 FEBRUARY 1995 Features BANDWIDTH: DC-15 GHZ HIGH ISOLATION : mmm > 50 dB NON-REFLECTIVE DESIGN Typical Performance General Description I I The HMC132 chip is a fast, broadband SPDT switch featuring high > 50 dB isola­

CH341A

Abstract: digital trainer schematic diagram laf 0001 CH3401 J0123 ccs ldl HP 3D6 000A75 X77H-X70H TO SI 788 48D
Contextual Info: H i/1 I - = - ^ • QE1F Device Quad E1 Framer TXC-03104 DATA SHEET FEATURES DESCRIPTION • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and

Contextual Info: M13E Device DS3/DS1 MUX/DEMUX, Extended Features TXC-03303 DATA SHEET FEATURES - = " ~ . = • Multiplexes/demultiplexes 28 DS1 signals to/from a DS3 signal. • M13 or C-bit parity mode operation • FEBE, C, or P-bit parity error insertion capability • DS3 idle signal generators

Contextual Info: E2/E3F Device 8-, 34 Mbit/s Framer TXC-03701 v DATA SHEET W FEATURES DESCRIPTION Framer for CCITT Recommendations: - G.742 8448 kbit/s - G.745 (8448 kbit/s) - G.751 (34368 kbit/s) - G.753 (34368 kbit/s) = The E2/E3 Framer (E2/E3F) is a CMOS VLSI device that provides the functions needed to frame a wideband

DAX 3S

Contextual Info: L3M Device Level 3 Mapper TXC-03452 DATA SHEET Product Preview i—— = = = = = = = = = = • SDH/SONET bus access: -Drop/add data byte access with clock, C1J1, SPE, and parity -Add bus interface timing derived from drop bus, add bus, or external timing

Contextual Info: • TRAN ^ k 1004152 0007020 104 ■ CUBIT Device «g*, »* jiüüM R. > ,.M V. CellBus Bus Switch TXC-05801 DATA SHEET DESCRIPTION FEATURES CUBIT is a single-chip solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus bus architecture. Such systems

Contextual Info: CDB Device Cell Delineation Block TXC-05150 DATA SHEET Preliminary DESCRIPTION ATM cell delineation per ITU 1.432 ATM cell rate adaptation Selectable cell output: FIFO, SARA, and UTOPIA Universal Test & Operations Physical Interface for ATM Identifies OAM F4 cells and non-user cells

Contextual Info: t r ä ^ s S w it c h P H A S T -1 D e v ic e SONET STS-1 Overhead Terminator TXC-06101 « DATA SHEET DESCRIPTION FEATURES Provides SONET interface to any type of payload Programmable STS-1 or STS-N modes Receive bit-serial STS-1 signal input to the Line Side using external reference frame pulse for

Contextual Info: ADMA-T1 Device DS1 to VT1.5 Async Mapper-Desync TXC-04001 DATA SHEET FEATURES . DESCRIPTION • Add/drop two DS1s from SONET bus through asynchronous VT1.5 mapping • Handles both STS and VT pointer tracking • Monitors bus parity, SONET loss of pointer, and

12-250-TP

Abstract: 1004155 824W170 12-250-T
Contextual Info: TITLE: SPECIFICATION CONTROL DRAWING PART IDENTIFIER: 12-250-TP DESCRIPTION: ASSEMBLY DWG: 1.0 PILL TERMINATION 1400214 SPECIFICATIONS: 1.1 ELECTRICAL: 1.1.1 IMPEDANCE: 50 OHMS NOMINAL. 1.1.2 FREQUENCY: DC-26.5 GHZ. 1.1.3 INPUT POWER MAX @ 25°C : (DERATED LINEARLY TO ZERO POWER @ 150°C)

FFD 455

Abstract: CA2270 FFD11 CA-575 marking code FFD CA278 5b S34 SARA-S
Contextual Info: Segmentation SARA Hardware Description SARA Chipset Technical Manual Chapter 3. Hardware Description 3.1 Segmentation SARA Hardware Description 3.1.1 Segmentation SARA Internal Block Description Figure 3-1 shows a block diagram o f the Segmentation S A R A chip.

Contextual Info: COBRA Device Constant Bit Rate ATM Adaptation Layer 1 TXC-05427 FEATURES i , —- = DATA SHEET Product Preview = DESCRIPTION COBRA C o nstant Bit Bate ATM Adaptation Layer 1 is a four-channel VLSI device that implements all of the functions needed for circuit emulation over ATM. Both

feme relay FT A 001 20 10

Abstract: feme cm a 001 12 feme relay
Contextual Info: SOT-1 E Device SONET STS-1 Overhead Terminator TXC-03011 DATA SHEET Programmable STS-1 or STS-N modes Receive bit-serial STS-1 signal input to the Line Side using external reference frame pulse input for STS-N applications Transmit bit-serial STS-1 signal output from the Line

Contextual Info: SOT-3 Device STM-1 /STS-3/STS-3c Overhead Terminator TXC-03003 DATA SHEET Preliminary FEATURES . = DESCRIPTION • Full overhead processing, compliant with ANSI and ITU-T standards = This SOT-3 SDH/SONET overhead terminator is a highly versatile, programmable device which performs

Contextual Info: COBRA Device Constant Bit Rate ATM Adaptation Layer 1 TXC-05427B DATA SHEET FEATURES = nFsrm PTinN — - = COBRA C onstant Bit Bate ATM Adaptation Layer 1 is a four-channel VLSI device that implements all of the functions needed for circuit emulation over ATM. Both

Contextual Info: ART Devices Advanced STS-1/DS3 Receiver/Transmitter ART: TXC-02020 44-Pin ARTE: TXC-02021 (68-Pin) DATA SHEET Product Preview FEATURES : ^ = = = = = = = = = ^ DESCRIPTION • Single chip line interface for DS3 and STS-1 The Advanced DS3/STS-1 Receiver/Transmitter (ART)

Contextual Info: QDS1F Device QUAD DS1 Framer TXC-03102 DATA SHEET Preliminary = • D4 SF, ESF including FDL support , and transparent framing modes DESCRIPTION m ssg.ss=saam .i i = • Detects, counts and forces line code errors (BPVs and excess zeros), CRC errors (ESF

Contextual Info: XBERT Device Bit Error Rate Generator Receiver TXC-06125 DATA SHEET FEATURES DESCRIPTION - = The Bit Error Rate Generator/Receiver XBERT VLSI device is a microprocessor-programmable multi-rate test pattern generator and receiver on a single chip. It is used for testing the performance of digital communica­

Contextual Info: JT2F Device 6 Mbit/s Framer TXC-03702 DATA SHEET FEATURES = DESCRIPTION • Framer for: - CCITT Recommendation G.704 - NTT-specified 6312 kbit/s format = The JT2 Framer JT2F is a CMOS VLSI device that provides the functions needed to frame a wideband payload to G.704 and the NTT-specified 6312 kbit/s