100-10L B2 Search Results

Contextual Info: *57 SGS-THOMSON TYPE S TD 6N 10L STD6N10L m N - CHANNEL ENHANCEMENT MODE LOW THRESHOLD POWER MOS TRANSISTOR V dss R DS on Id 100 V < 0 .4 5 Ü 6 A • • . . ■ . . ■ TYPICAL RDS(on) = 0.4 Cl AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100°C

Contextual Info: b2E D MOSEL-VITELIC MOSEL-VITELIC • 33533^1 0 0 0 2 D 7 3 SST « M O V I V53C405 1 M X 4 B IT 4 CAS CMOS DYNAMIC RAM HIGH PERFORMANCE V53C405 Max. RAS Access Time, (tRAn ADVANCED INFORMATION 60/60L 70/70L 80/80L 10/10L 100 ns 60 ns 70 ns 80 ns Max. Column Address Access Time, (tnAA)

YM 3533

Contextual Info: bEE D MOSEL-VITELIC MOSEL-VITELIC • b3533^1 Q0QS3MS 7Ô3 ■ M O V I V400J8/9 4M X 8, 4M X 9 B IT FA ST PAGE MODE CMOS DYNAMIC RAM M EM ORY MODULE HIGH PERFORMANCE, LO W POWER HIGH PERFORMANCE V400J8/9 PRELIMINARY 70/70L 80/80L 10/10L 70 ns 80 ns 100 ns

Q001

Abstract: DHR48 V53C464
Contextual Info: bSE M O SEL-VITELIC T> m b 3 S 3 3 T l Ü G Q lflM b b T l V53C464A FAMILY HIGH PERFORMANCE; LOW POWER 64K X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM 60/60L 70/70L 80/80L 10/10L Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns 100 ns Max. Column Address Access Time, (tCAA)

K2100

Abstract: STD6N10L
Contextual Info: S G S - T H O M S O N ¿ 5 S T D 6N 1 0 L ¡m e ra « 7 N - CHANNEL ENHANCEMENT MODE LOW THRESHOLD POWER MOS TRANSISTOR TYP E S TD 6N 10L V dss RDS on Id 100 V < 0.4 5 C l 6 A • . ■ . . . ■ . TYPICAL RDS(on) = 0.4 Q. AVALANCHE RUGGED TECHNOLOGY

Contextual Info: bSE ]> m o s e l -vi tel ic MOSEL- VITELIC • bBSBBTl DGQnñS V53C664 6 4 K x 16 B IT F A S T P A G E M O D E B Y T E W R ITE C M O S D Y N A M IC R A M V53C664 P R E L IM IN A R Y 80/80L 10/10L Max. RAS Access Time, tRAn 80 ns 100 ns Max. Column Address Access Time, (tr s 4)

micrel sy55852

Abstract: SY55852
Contextual Info: RELIABILITY REPORT DATE: 6/3/04 QUALITY ENG : DANA TRINH PURPOSE: Qualify HL BASE ARRAY QUAL VEHICLES PACKAGE TYPE : ASSEMBLY LOCATION D/C # LOT # FAB # ARRAY PROCESS SY55851 10L MSOP UNISEM 243B B206003M09 MICREL HL ASSET 1 SY55854 10L MSOP EPAD UNISEM 04SE

m5m5256

Contextual Info: MITSUBISHI LS Is b24Tfl2S DDSMSn 14T • MIT1 M5M5256BVP,RV-70L,-85L,-10L,-12L,-15L, -70LL,-85LL,-10LL,-12LL,-15LL 262144-BIT 32768-WORD BY 8-BIT CMOS STATIC RAM DESCRIPTION The M 5M 5256B VP , RV are 26 2 1 4 4 -b it CMOS static RAMs organized as 32768-w ords by 8-bit. They are fabricated using

Contextual Info: • b24Tfl2S 0 0 2 4 2 1 4 bb? ■ M I T I M 5 M MITSUBISHILSIs 5 2 5 6 B P ,F P ,K P - 7 0 ,- 8 5 ,- 1 0 ,- 1 2 ,-1 5 ,- 7 0 L ,- 8 5 L , - 1 0 L ,- 1 2 L ,- 1 5 L ,- 7 0 L L ,- 8 5 L L ,- 1 0 L L ,- 1 2 L L ,- 1 5 L L 262144-BIT 32768-WORD BY 8-BIT CMOS STATIC RAM

M51008P

Abstract: M5M51008P
Contextual Info: L IE D b24^fl25 D O IIIB ? • M IT I MITSUBISHI LSIs M5M51008P,FP-70,-85,-10,-12,-70L,-85L, •101,-12L,-7011,-8511,-1011,-1211 1048576-BIT 1 31072-WORD BY 8-BIT CMOS STATIC RAM MITSUBISHI DESCRIPTION (MEMORY/ASIC) The M 5M 51008P, FP are 1,048,576-bit CMOS static RAM

TC55257BPI-10L

Contextual Info: 32,768 W O R D S x 8 B IT S T A T I C R A M PRELIMINARY D ESC RIPT IO N The TC55257BPI is 262,144 bit static ramdom access memory organized as 32,768 words by 8 bits using CMOS technology, and operated from a single 5V supply. Advanced circuit techniques provide

TC551001

Contextual Info: TOSHIBA TC551001 BPI/BFI/BFTI/BTRI/BSTI/BSRI-85L,-10L TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 131,072-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC551001BPI/BFI/BFTI/BTRI/BSTI/BSRI is a 1,048 576-bit static random access memory SRAM organized as 131,072 words by 8 bits. Fabricated using Toshiba’s CMOS Silicon gate process technology, this

Contextual Info: blE » • b24 T Ô2 5 0 Q 2 G b T 3 TSfl ■ MITl MITSUBISHI LSIs MH2M08TNA-85L,-10L,-12L,-15L/ MH2M08TNA-85H,-10H,-12H,-15H 1 6 7 7 7 2 1 6 -B IT 2 0 9 7 1 5 2 -W O R D BY 8 -B IT C M 0S STATIC RAM MITSUBISHI ( M E M OR Y/ AS IC ) DESCRIPTION T h e M H 2 M 0 8 T N A is a 1 6 7 7 7 2 1 6 bits C M O S s ta tic R A M

Contextual Info: MITSUBISHI LSIs M5M51008BP,FP,VP,RV,KV,KR-55L, -70L, -10L, -55LL,-70LL,-10LL 1048576-BIT 131072-WQRD BY 8-BITJCMOS STATIC RAM DESCRIPTION The M5M51008BP,FP,VP,RV,KV,KR are a 1048S76-bit CMOS static RAM organized as 131072-word by 8-bit which are fabricated using high-performance triple poiysiiicon CMOS

Diode smd f6

Contextual Info: MITSUBISHI LSIs M5M51R16AWG -10L, -12L, -15L, -10H, -12H, -15H 1048576-BIT 65536-WORD BY 16-BIT CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M51R16AWG is a 1048576-bit CMOS static RAM organized as 65536 words by 16-bits, which are fabricated using

8L-10L

Contextual Info: MITSUBISHI LSIs SDRAM Rev.1.3 Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit

8L-10L

Contextual Info: MITSUBISHI LSIs SDRAM Rev.1.3 Mar98 M5M4V64S20ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 4194304-WQRD x 4-BIT) Synchronous DRAM Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit

8L-10L

Contextual Info: MITSUBISHI LSIs ^-, ._ SDRAM Rev.1.3 Mar'98 M5M4V64S30ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit

5m41000

Contextual Info: MITSUBISHI LSIs M5M41000BP,J,L,VP,RV-7L,-8L,-10L FAST PAGE MODE 1 0 4 8 5 7 6 -B IT 1 0 4 8 5 7 6 -W 0 R D BY 1-BIT DYNAMIC RAM DESCRIPTION This is a fam ily o f 1048576-w ord by 1-bit dynam ic RAMs, PIN CONFIGURATION (TOP VIEW) fabricated w ith the high performance CMOS process, and

Contextual Info: bSMTÔES aaSME^â flbb • M I T I MITSUBISHILSIs M5M5408P, FP,TP,RT-55,-70,-85,-10,-55L,-70L,-85L,-1 OL, -55LL,-70LL,-85LL,-1 OLL 4194304-BIT 524288-WOBD BY 8-BIT CMOS STATIC RAM p f i 1W» *" al hW'>» N0"fpa«t"6t" Soff'6 DESCRIPTION The M5M5408 is 4194304-bit CMOS static RAM organized

Contextual Info: MITSUBISHI LS Is M5M5408P,FP,TP,RT-55L,-70L,-10L, -55LL,-70LL,-1 OLL 4194304-BIT 524288-WORD BY 8-BIT CMOS STATIC RAM DESCRIPTION The M5M5408 is 4194304-bit CMOS static RAM organized as 524288-words by 8-bit, fabricated using high-performance quadruple-polysilicon and double metal CMOS technology.

Contextual Info: MITSUBISHI LSIs M5M51008BP,FP,VP,RV-55L, -70L, -10L, -55LL,-70LL,-1 OLL 1048576-BIT 131Q72-WOR D BY 8-BIT CMOS STATIC RAM DESCRIPTION The M5M51008BP,FP,VP,RV are a 1048576-bit CMOS static PIN CONFIGURATION (TOP VIEW) • V RAM organized as 131072-word by 8-bit which are fabricated

Contextual Info: MITSUBISHI LS Is M5M5255BP,FP,KP-70,-85,-10,-12,-70L,-85L, -10L,-12L,-70LL,-85LL,-10LL,-12LL 262144-BIT 32768-WORD BY 8-BIT CMOS STATIC RAM DESCRIPTION The M5M5255BP, FP, KP is a 262144-bit CMOS static FiAM organized as 32768-words by 8-bits which is fabricated using

Contextual Info: blE J> m b E MT ÛE S Q O l T BT b 443 • n i T l I MITSUBISHI LSIs M5M44100AWJ,J,L,TP,RT-6L,-7L,-8L,-10L MITSUBISHI I M EM OR Y/ AS IC FAST PAGE MODE 4 1 9 4 3 0 4 -B IT (4 1 9 4 3 0 4 -W O R D BY 1-BIT)DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW)