1 BIT SRAM Search Results

Contextual Info: MITSUBISHI LSIs M 5 M 4 V 1 6 1 6 9 T P - 1 0 ,- 1 2 ,- 1 5 16M CDRAM16M 1024K-WORD BY 16-BIT CACHED DRAM WITH 16K(1024-WORD BY 16-BIT)SRAM DESCRIPTION The M5M4V16169TP is a 16M-bit Cached DRAM which integrates input registers, a 1048576-word by 1 6 - bit

m5m5v1132

Contextual Info: MITSUBISHI LSIs M 5 M 5 V 1 1 3 2 F P -6 ,-7 ,-8 ,-1 0 , -7 L ,-8 L ,-1 0 L 1048576-BIT 32768-WQRP BY 32-BIT SYNCHRONOUS BURST SRAM DESCRIPTION The M5M5V1132FP is a family of 1M bit synchronous SRAMs organized as 32768-words of 32-bit. The M5M5V1132FP provides

M5M4V4169TP20

Abstract: mitsubishi cdram M5M4V4169TP sram 3.3 16bit
Contextual Info: MITSUBISHI LSIs M5M4V4169TP-15,-20 4M 256K-WORD BY 16-BIT CACHED DRAM WITH 16K(1024-WORD BY 16-BIT)SRAM DESCRIPTION The M5M 4V4169TP is a 4 M - b it Cached DRAM which integrates input registers, a 262, 1 44-w o rd by 1 6 - bit dynamic memory array and a 1 0 2 4 -word by 1 6 - bit static

sram 3.3 16bit

Contextual Info: MITSUBISHI LSIs M5M4V4169TP-15,-20 4M 256K-WORD BY 16-BIT CACHED DRAM WITH 16K(1024-WORD BY 16-BIT)SRAM DESCRIPTION The M5M4V4169TP is a 4 M - b it Cached DRAM which integrates input registers, a 262, 1 4 4 - word by 1 6 - bit dynamic memory array and a 1 0 2 4 -word by 1 6 - bit static

M5M4V16169TP-10

Abstract: mitsubishi scr
Contextual Info: MITSUBISHI LSIs M 5M 4V16169TP-10,-12,-15,-20 16M 1M-W0RD BY 16-BIT CACHED DRAM WITH 16K(1024-WORD BY 16-BIT)SRAM DESCRIPTION The M 5 M 4V 161 69T P is a 16M - bit Cached DRAM which integrates input registers, a 1 0 4 8 5 7 6 - w ord by 1 6 - bit dynamic m em ory array and a 1 0 2 4 - w ord by 1 6 - bit static

K7J321882M

Abstract: K7J321882M-FC16 K7J321882M-FC20 K7J321882M-FC25 K7J323682M K7J323682M-FC16 K7J323682M-FC20 K7J323682M-FC25
Contextual Info: K7J323682M K7J321882M K7J320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 200 1 Advance 0.1 1. 2. 3. 4.

Contextual Info: K7J323682M K7J321882M K7J320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 200 1 Advance 0.1 1. 2. 3. 4.

Contextual Info: MITSUBISHI LSIs M5M4V4169TP-15,-20 4M 256K-WORD BY 16-BIT CACHED DRAM WITH 16K(1024-WORD BY 16-BIT)SRAM DESCRIPTION The M5M4V4169TP is a 4 M - b it Cached DRAW which integrates input registers, a 262, 1 4 4 - word by 1 6 - bit dynamic memory array and a 1024-w o rd by 1 6 - bit static

Contextual Info: K7I323684M K7I321884M K7I320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1.

AC 220 to DC 14v 10A

Contextual Info: K7I323682M K7I321882M K7I320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1.

Contextual Info: DATA SHEET_ MOS INTEGRATED CIRCUIT UPD43 4 0 0 1 A 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT Description The ^¡PD434001A is a high speed, low power, 4,194,304 bits 4,194,304 words by 1 bit CMOS static RAM. Operating supply voltage is 5.0 V ± 0.5 V.

Contextual Info: K7J323682M K7J321882M K7J320882M 1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 200 1 Advance 0.1 1. 2. 3. 4. 5. 6. Dec, 14 2001

samsung pd

Abstract: K7I320884M K7I321884M K7I321884M-FC16 K7I321884M-FC20 K7I321884M-FC25 K7I323684M K7I323684M-FC16 K7I323684M-FC20 K7I323684M-FC25
Contextual Info: K7I323684M K7I321884M K7I320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1.

K7I321882M-FC25

Abstract: K7I323682M-FC25 T 3H K7I320882M K7I321882M K7I321882M-FC16 K7I321882M-FC20 K7I323682M K7I323682M-FC16 K7I323682M-FC20
Contextual Info: K7I323682M K7I321882M K7I320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1.

K7R320884M

Abstract: K7R321884M K7R321884M-FC20 K7R321884M-FC25 K7R323684M K7R323684M-FC16 K7R323684M-FC20 K7R323684M-FC25
Contextual Info: K7R323684M K7R321884M K7R320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 QDR TM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify.

K7R641882M-FC20

Abstract: K7R643682M-FC20 K7R641882M-FC16 K7R643682M-FC16 K7R641882M-FC25 K7R643682M-FC25 K7R643682M K7R640982M K7R641882M K7R641882MFC25
Contextual Info: K7R643682M K7R641882M K7R640982M Preliminary 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit, 8Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Sep, 14 2002 Advance 0.1 1. Update AC timing characteristics.

mask rom

Contextual Info: MOS INTEGRATED CIRCUIT µPD26411 1 M-BIT SRAM AND 2M-BIT MASK ROM COMBO CHIP SRAM 128K-WORD BY 8-BIT / MASK ROM (256K-WORD BY 8-BIT) Please consult with our sales offices for data sheet.

K7R320884M

Abstract: K7R321884M K7R321884M-FC20 K7R321884M-FC25 K7R323684M K7R323684M-FC16 K7R323684M-FC20 K7R323684M-FC25 Q34D
Contextual Info: K7R323684M K7R321884M K7R320884M 1Mx36 & 2Mx18 & 4Mx8 QDR TM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify.

Contextual Info: K7R323684M K7R321884M K7R320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 QDRTM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify.

IR 10D 8A

Contextual Info: K7R323684M K7R321884M K7R320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 QDRTM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify.

Contextual Info: K7R323684M K7R321884M K7R320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 QDR TM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify.

JTAG 10P

Abstract: K7R641882M-FC25 K7R640982M-FC25 K7R643682M-FC20
Contextual Info: K7R643682M K7R641882M K7R640982M Preliminary 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit, 8Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Sep, 14 2002 Advance 0.1 1. Update AC timing characteristics.

mitsubishi cdram

Abstract: M5M4V16169TP-10
Contextual Info: MITSUBISHI LSIs M 5 M 4 V 1 6 1 6 9 T P -1 0 ,-1 2 ,-1 5 16M CDRAM16M 1024K-WORD BY 16-BIT CACHED DRAM WITH 16K(1024-WORD BY 16-BIT)SRAM DESCRIPTION The M 5 M 4 V 1 6 1 6 9 T P is a 1 6 M -b it Cached DRAM which integrates input registers, a 1 0 4 8 5 7 6 - w ord by 1 6 - bit

Contextual Info: K7I323684M K7I321884M K7I320884M 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. 2. 3. 4. 5.