1 BIT SRAM Search Results

K7J321882M

Abstract: K7J321882M-FC16 K7J321882M-FC20 K7J321882M-FC25 K7J323682M K7J323682M-FC16 K7J323682M-FC20 K7J323682M-FC25
Contextual Info: K7J323682M K7J321882M K7J320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 200 1 Advance 0.1 1. 2. 3. 4.

Contextual Info: K7I323684M K7I321884M K7I320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1.

AC 220 to DC 14v 10A

Contextual Info: K7I323682M K7I321882M K7I320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1.

K7R320884M

Abstract: K7R321884M K7R321884M-FC20 K7R321884M-FC25 K7R323684M K7R323684M-FC16 K7R323684M-FC20 K7R323684M-FC25 Q34D
Contextual Info: K7R323684M K7R321884M K7R320884M 1Mx36 & 2Mx18 & 4Mx8 QDR TM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify.

Contextual Info: K7R323684M K7R321884M K7R320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 QDRTM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June 30, 2001 Advance 0.1 1. Package dimension modify.

Contextual Info: K7I323684M K7I321884M K7I320884M 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. 2. 3. 4. 5.

Contextual Info: K7I323682M K7I321882M K7I320882M 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. 2. 3. 4. 5.

10D-11

Abstract: K7R160982B K7R160982B-FC16 K7R160982B-FC20 K7R161882B K7R161882B-FC16 K7R161882B-FC20 K7R163682B K7R163682B-FC16 K7R163682B-FC20
Contextual Info: K7R163682B K7R161882B K7R160982B 512Kx36 & 1Mx18 & 2Mx9 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002 Advance 0.1 1. Change the Boundary scan exit order.

Contextual Info: K7R163684B K7R161884B K7R160884B Preliminary 512Kx36 & 1Mx18 & 2Mx8 QDR TM II b4 SRAM Document Title 512Kx36-bit,1Mx18-bit, 2Mx8-bit QDR TM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17. 2002 Advance 0.1 1. Change the Boundary scan exit order.

K7R320982M-FC20

Abstract: K7R323682M-FC20 K7R320982M K7R321882M K7R321882M-FC16 K7R321882M-FC20 K7R323682M K7R323682M-FC16 4MX9
Contextual Info: K7R323682M K7R321882M K7R320982M 1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001 Advance 0.1 1. 2. 3. 4. 5. 6. Dec. 5 2001

D434001

Abstract: D434001ALG5
Contextual Info: DATA SHEET_ MOS INTEGRATED CIRCUIT juPD434001 AL 4M -BIT CMOS FAST SRAM 4M-W ORD BY 1-BIT Description The /¿PD434001AL is a high speed, low power, 4,194,304 bits 4,194,304 words by 1 bit CMOS static RAM. Operating supply voltage is 3.3 V ± 0.3 V.

K7R161884B

Abstract: K7R161884B-FC25 K7R161884B-FC30 K7R163684B K7R163684B-FC16 K7R163684B-FC20 K7R163684B-FC25 K7R163684B-FC30
Contextual Info: K7R163684B K7R161884B K7R160884B Preliminary 512Kx36 & 1Mx18 & 2Mx8 QDR TM II b4 SRAM Document Title 512Kx36-bit,1Mx18-bit, 2Mx8-bit QDR TM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17. 2002 Advance 0.1 1. Change the Boundary scan exit order.

Contextual Info: K7I323684M K7I321884M K7I320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. Pin name change from DLL to Doff.

Contextual Info: K7I323684M K7I321884M K7I320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. Pin name change from DLL to Doff.

K7I323682M-FC25

Abstract: K7I321882M-FC16
Contextual Info: K7I323682M K7I321882M K7I320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. Pin name change from DLL to Doff.

Contextual Info: TOSHIBA TC55V11601FT-15 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 16,777,216-WORD BY 1-BIT CMOS STATIC RAM DESCRIPTION The TC55V11601FT is a 16,777,216-bit high speed static random access memory SRAM organized as 16,777,216 words by 1 bit. Fabricated using CMOS technology and advanced circuit techniques to provide high

Contextual Info: FUJITSU MIC ROE LECTRONIC S 47E D • 374^71^ OOlflflD? 1 ■ May 1990 Edition 1.0 FUJITSU DATA SHEET ~ p 4 tr-J L 3 -Q MB81C81A-25/-35 CMOS 256K-BIT HIGH-SPEED SRAM 256K Words x 1 Bit High-Speed CMOS Static Random AccfeSs Memory Th» Fujitsu MB81C81A is a 262,144 words x 1 bit static random access memory

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT MPD4 3 1 2 3 1 L 1M-BIT CMOS SYNCHRONOUS FAST SRAM 32K-WORD BY 32-BIT PIPELINED OPERATION Description The ,uPD431231L is a 32,768-word by 32-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell.

marking CS nec

Abstract: 32-PIN UPD444001LE-12
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD444001 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT Description The µPD444001 is a high speed, low power, 4,194,304 bits 4,194,304 words by 1 bit CMOS static RAM. Operating supply voltage is 5.0 V ± 0.5 V. The µPD444001 is packaged in 32-pin PLASTIC SOJ.

32-PIN

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT PD444001 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT Description The μPD444001 is a high speed, low power, 4,194,304 bits 4,194,304 words by 1 bit CMOS static RAM. Operating supply voltage is 5.0 V ± 0.5 V. The μPD444001 is packaged in 32-pin PLASTIC SOJ.

CompactCellTM Static RAM

Contextual Info: PRELIMINARY Am45DL6408G Stacked Multi-Chip Package MCP Flash Memory and SRAM 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) CompactCellTM Static RAM DISTINCTIVE CHARACTERISTICS

M420000000

Abstract: FSB073 3FE00
Contextual Info: PRELIMINARY Am42DL640AG Stacked Multi-Chip Package MCP Flash Memory and SRAM 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features • Minimum 1 million write cycles guaranteed per sector

Contextual Info: H Y 6 7 V 1 6 1 1 0 /1 1 1 HYUNDAI 64K x 16 Bit SYNCHRONOUS CMOS SRAM PRELIM INARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a

DS42515

Contextual Info: DS42515 Stacked Multi-Chip Package MCP Flash Memory and SRAM Am29DL164D Bottom Boot 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS