0x0000020C
Abstract: 0x00000158 0x0000014C 0x00000154 0x00000210 asynchronous fifo vhdl xilinx slot machine block diagram vhdl 0x00000060 0x00000048 0x00000218
Contextual Info: FlexRay v1.1 DS544 May 17, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE FlexRay™ controller implements the FlexRay communication protocol as defined in the FlexRay Protocol Specification v2.1 Rev A. The FlexRay controller implementation supports a single communication channel. This document defines the architecture
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ds5440x0000020c0x000001580x0000014c+70x000001540x00000210asynchronous fifo vhdl xilinxslot machine block diagram vhdl0x000000600x000000480x00000218
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flexray PROTOCOL
Abstract: 0x0000020C slot machine block diagram vhdl 0x00000204 0x00000158 Spartan 3E VHDL code 0x00000338 0x0000014C 0x00000210
Contextual Info: - DISCONTINUED PRODUCT 0 FlexRay v1.1 DS544 May 17, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE FlexRay™ controller implements the FlexRay communication protocol as defined in the FlexRay Protocol Specification v2.1 Rev A. The FlexRay
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ds544flexray protocol0x0000020cslot machine block diagram vhdl+60x000002040x00000158spartan 3e vhdl code0x000003380x0000014c0x00000210
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TMS320C64xx
Abstract: 6713 SPRU266 SPRU401J pulse code interval encoding using c6713 pulse code interval encoding using c6713 timer 458 TIMER CIRCUIT COLLECTION B536 rld bh-16 SPRU401 TMS320C64xx cpu
Contextual Info: TMS320C6000 Chip Support Library API Reference Guide Literature Number SPRU401J August 2004 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any
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tms320c6000spru401jindex-11b-416+10index-12tms320c64xx6713 spru266pulse code interval encoding using c6713pulse code interval encoding using c6713 timer458 timer circuit collectionb536rld bh-16spru401tms320c64xx cpu
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AN1780
Abstract: DSP56300 DSP56301 DSP56305
Contextual Info: MOTOROLA Order by AN1780/D Motorola Order Number Rev. 0 , 11/98 Semiconductor Application Note Contents DSP563xx HI32 As A PCI Agent The Host Interface (HI32) is a fast 32-bit wide parallel host port that can directly connect to the host bus. The HI32 is a
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an1780/ddsp563xx32-bitdsp56301+4dsp56305office141an1780dsp56300
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0x00000378
Abstract: 0x0000043C
Contextual Info: - DISCONTINUED PRODUCT XPS FlexRay Controller v1.00a DS636 October 30, 2007 Product Specification Introduction LogiCORE Facts The Xilinx FlexRay LogiCORE product specification defines the architecture and features of the Xilinx FlexRay controller. This document also defines the
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DSP56300
Abstract: DSP56301 DSP56305
Contextual Info: Freescale Semiconductor, Inc. MOTOROLA Order by AN1780/D Motorola Order Number Rev. 0 , 11/98 Semiconductor Application Note Contents DSP563xx HI32 As A PCI Agent The Host Interface (HI32) is a fast 32-bit wide parallel host port that can directly connect to the host bus. The HI32 is a
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SPRU401C
Abstract: TMS320C64xx cpu C6000 C6201 SPRU189 SPRU190 TMS320C6000
Contextual Info: TMS320C6000 Chip Support Library API User’s Guide Literature Number SPRU401C October 2001 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at
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tms320c6000spru401ctms320c64xx cpuc6000+3c6201spru189spru190
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ESI 2150 manual
Abstract: DSP56300 DSP56301 DSP56305
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor Order by AN1780/D Motorola Order Number Rev. 0 , 11/98 Contents DSP563xx HI32 As A PCI Agent The Host Interface (HI32) is a fast 32-bit wide parallel host port that can directly connect to the host bus. The HI32 is a
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an1780/ddsp563xx32-bitdsp56301+3dsp56305esi 2150 manualdsp56300
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0x000000F9
Abstract: XAPP515 XAPP516 0xABCDEF12 0x300000FF
Contextual Info: Application Note: Embedded Processing R XAPP515 v1.0 May 19, 2006 Using Xilinx m4 Functions to Write Bus Functional Language Stimuli for CoreConnect Buses Author: Lester Sanders Summary This application note provides definitions and examples of Xilinx developed m4 functions used
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xapp5150x0000000f0xff0000000x00ff0000+90x0000ff000x000000ff0xffff00000x0000ffff0x00000000xapp5160x000000f90xabcdef120x300000ff
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