0TBL722 Search Results

XD13

Contextual Info: TMX320C30, TMS320C30 DIGITAL SIGNAL PROCESSORS SPRS032-APRIL 1996 High-Performance Floating-Point Digital Signal Processor DSP - TMX320C30-50 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS - TMS320C30-40 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS

variable PWM by using dsp TMS320F240

Abstract: TMS320F240 "space vector" tms320 PWM by using dsp TMS320F240 SEG CT 7800 TMS320C240 F240 TMS320 TMS320C25 TMS320X240
Contextual Info: TMS320C240, TMS320F240 DSP CONTROLLERS High-Performance Static CMOS Technology Includes the T320C2xLP Core CPU - Source Code Compatible With TMS320C25 - Upwardly Compatible With TMS320C5x - 132-Pin Plastic Quad Flat Package - 50-ns Instruction Cycle Time Industrial Temperature Standard,

Contextual Info: TMS320C5X, TMS320LC5X DIGITAL SIGNAL PROCESSORS SPRS030-APRIL 1995 • Powerful 16-Bit TMS320C5X CPU • Multiple Phase-Locked Loop PLL Clocking Options (x1, x2, x3, x4, x5, x9 Depending on Device) • 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V

40d27

Abstract: C3133
Contextual Info: TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS _ S P R S Q 35A -M A R C H 1996 - REVISED JULY 1997 * High-Performance Floating-Point Digital Signal Processor DSP : f - TMS320C31-60 (5 V) 33-ns Instruction Cycle Time 330 MOPS, 60 MFLOPS, 30 MIPS

TMS320F206 load program

Abstract: C2xx DCm240 EZ76 HCL 0300 C203 F206 TMS320 TMS320C203 TMS320C209
Contextual Info: TMS320F206 DIGITAL SIGNAL PROCESSOR • High-Performance Static CMOS Technology 32-Bit ALU/Accumulator • Includes the T320C2xLP Core CPU 16 x 16-Bit Multiplier With a 32-Bit Product • TMS320F206 is a Member of the TMS320C2xx Generation That Also Includes the TMS320C203, TMS320C204,

ic isl 887

Abstract: T85 1e4 Switch TMS320C80 MP 1008 es MIP 289 C8050 AH-34 alu module for 32 bit processor GLC 555 texas instrument
Contextual Info: TMS320C80 DIGITAL SIGNAL PROCESSOR S P R S Q 2 3 A -JULY 1994 - R E VIS ED MARCH 1996 • Single-Chip Parallel Multiple Instruction/Multiple Data MIMD DSP • More Than Two Billion RISC-Equivalent Operations per Second • Master Processor (MP) - 32-Bit Reduced Instruction Set

Contextual Info: TMS34020, TMS34020A GRAPHICS PROCESSORS SPVS004D - MARCH 1990 - REVISED NOVEMBER 1993 * Instruction Cycle Time - 100 ns . . . TMS34020A-40 - 1 2 5 n s . . .TMS34020-32 - 125 n s . . . TMS34020A-32 145-PIN GB PACKAGE TOP VIEW A B C D E F G H J • Fully Programmable 32-Bit

LTS 547 EH

Abstract: LTS 543 210HL SXM 08 43A1h lts 543 pin configuration AAIBB ACC20 lts 547 ar 719 C203
Contextual Info: Chapter 7 Assembly Language Instructions The 'C2xx instruction set supports numerically intensive signal-processing op­ erations as well as general-purpose applications such as multiprocessing and high-speed control. The ’C2xx instruction set is compatible the ’C2x instruction