07AUG2001 Search Results

Contextual Info: M74HC09 Quad 2-input and gate open drain Features • HIgh Speed: tPD = 7ns (Typ.) at VCC = 6V ) s ( t c u d o ) r s ( P t c e t u e d l o o r s Description P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b OOrder codes e t e l

Contextual Info: M41ST84W 3.0/3.3 V I2C serial RTC with 44 bytes of NVRAM and supervisory functions Not recommended for new design Features • Automatic battery switchover and deselect – Power-fail deselect, VPFD = 2.60 V nom – Switchover, VSO = 2.50 V (nom) ■ 400 kHz I2C serial interface

M48T512V

Abstract: M48T512Y
Contextual Info: M48T512Y M48T512V 5.0 or 3.3 V, 4 Mbit 512 Kbit x 8 TIMEKEEPER SRAM Features • Integrated ultra-low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Automatic power-fail chip deselect and write

M41ST85W

Abstract: M4T28-BR12SH1 M4T32-BR12SH1 M4T32-BR12SH6 SOH28
Contextual Info: M41ST85W 3.0/3.3V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor Features • ■ SNAPHAT SH battery & crystal Automatic battery switchover and WRITE protect for: – Internal serial RTC and – External low power SRAM (LPSRAM)

yw-360-02b

Abstract: TRANSFORMER EI25 10 XFMR 4 TURN HORIZONTAL POWER COUPLING 822my SS11V top22x TOP243 YIH-HWA BOBBIN ENTERPRISE KME10VB47 TM501
Contextual Info: Title Engineering Prototype Report for EP-18 10 W, Multiple Output, Isolated Power Supply with TOPSwitch-GX Input Voltage Key Specifications Output Voltages and Current Output Power Efficiency P.I. Device 85-265 VAC 3.3 V, 1.5 A 5 V, 0.9 A 30 V, 0.03 A

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KDS 32kHZ crystal

Abstract: quartz crystal kds 70 AN1572 M41ST84W AN1012 AI005
Contextual Info: M41ST84W 3.0/3.3 V I2C serial RTC with 44 bytes of NVRAM and supervisory functions Not recommended for new design Features • Automatic battery switchover and deselect – Power-fail deselect, VPFD = 2.60 V nom – Switchover, VSO = 2.50 V (nom) ■ 400 kHz I2C serial interface

TECHNICAL SPECIFICATION DATA SHEET GOLD 705

Abstract: M41ST85W M4T28-BR12SH1 M4T32-BR12SH1 M4T32-BR12SH6 SOH28 AN934 24JAN NVRAM
Contextual Info: M41ST85W 3.0/3.3 V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor Features SNAPHAT SH battery & crystal • Automatic battery switchover and WRITE protect for: – Internal serial RTC and – External low power SRAM (LPSRAM) ■

AN1012

Abstract: M41ST84W block diagram of energy saving ABE smd
Contextual Info: M41ST84W 3.0/3.3 V I2C serial RTC with 44 bytes of NVRAM and supervisory functions Features • Automatic battery switchover and deselect – Power-fail deselect, VPFD = 2.60 V nom – Switchover, VSO = 2.50 V (nom) ■ 400 kHz I2C serial interface ■ 3.0/3.3 V operating voltage

M48T512Y

Abstract: STMicroelectronics 1N58 5747
Contextual Info: M48T512Y M48T512V 5.0 or 3.3 V, 4 Mbit 512 Kbit x 8 TIMEKEEPER SRAM Not recommended for new design Features • Integrated ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded year, month, day, date, hours,

Contextual Info: 47,04 38.03 1.385X24=33.24 D —(—(— 7 7 - \^ ^ 0- 0- 0- 0- 0-0- 0-0- 0- 0- ^ ^ / / - I 5 - I 8.54±0.25 CD 1 1.385TYP. 12 25 24 10 23 9 22 8 21 7 20 6 19 5 18 4 17 3 16 2 15 1.9 V- 11 -4 0 UNC A 47.04 iO.25 RECOMMENDED P. C. B LAYOUT (T = 1 .0 0 m m )

JESD97

Abstract: M74HC09 M74HC09B1R M74HC09M1R M74HC09RM13TR TSSOP14
Contextual Info: M74HC09 Quad 2-input and gate open drain Features • HIgh Speed: tPD = 7ns (Typ.) at VCC = 6V ■ Low power dissipation: ICC = 1µA (Max.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28 % VCC (Min.) DIP-14 ■ Balanced propagation delays: tPLH ≅ tPHL

AMP PBT GF20 connector

Abstract: ejot torque
Contextual Info: 7 8 THIS DRAWING IS UNPUBLISHED. VERTRAULICHE UNVEROEFFENTLICHTE ZEICHNUNG C COPYRIGHT 2000 RELEASED FOR PUBLICATION FREI FUER VEROEFFENTLICHUNG ALL RIGHTS RESERVED. ALLE RECHTE VORBEHALTEN. Tyco Electronics AMP GmbH 6 2001- - 5 4 3 2 LOC MATED WITH: PASSEND ZU:

M48T512V

Abstract: M48T512Y 03-DEC-1999
Contextual Info: M48T512Y M48T512V 5.0 or 3.3 V, 4 Mbit 512 Kbit x 8 TIMEKEEPER SRAM Features • Integrated ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Automatic power-fail chip deselect and WRITE

M4T32-BR12SH6

Contextual Info: M41ST85W 3.0/3.3 V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor Features SNAPHAT battery & crystal • Automatic battery switchover and WRITE protect for: – Internal serial RTC and – External low power SRAM LPSRAM ■ 400 kHz I2C serial interface

Contextual Info: M41ST85W 3.0/3.3 V I2C combination serial RTC, NVRAM supervisor and microprocessor supervisor Features • ■ SNAPHAT battery & crystal Automatic battery switchover and WRITE protect for: – Internal serial RTC and – External low power SRAM LPSRAM 400 kHz I2C serial interface

Contextual Info: 2 THIS £L DRAWING IS UNPUBLISHED. BY C O P Y R I G H T 20 RELEASED TYCO ELECTRONICS CORPORATION. ALL FOR 20 PUBLICATION R 1G H T S LOC DIST R E V ISIONS AD 00 RESERVED. LTR DESCRIPTION R E L E A S E D PER 0 G 3 C - 0 0 7 8 - 0 3 0G 3 C - 0 7 5 6 - 0 4 R E V I S E D PER ECO - 0 9 - 0 2 5 6 9 9

Contextual Info: M48T512Y M48T512V 5.0 or 3.3 V, 4 Mbit 512 Kbit x 8 TIMEKEEPER SRAM Not recommended for new design Features • Integrated ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded year, month, day, date, hours,

JESD97

Abstract: M74HC390 M74HC390B1R M74HC390RM13TR
Contextual Info: M74HC390 Dual decade counter Features • HIgh Speed: fMAX = 79MHz Typ. at VCC = 6V ■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28 % VCC (Min.) ■ Balanced propagation delays: tPLH ≅ tPHL ■ Wide operating voltage range:

Contextual Info: M74HC390 Dual decade counter Features • HIgh Speed: fMAX = 79MHz Typ. at VCC = 6V ■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28 % VCC (Min.) ) s t( c u d DIP-16 ■ Balanced propagation delays: tPLH ≅ tPHL