027Q Search Results

Contextual Info: THIS DRAWING IS C O P Y R IG H T U N P U B L IS H E D . 19 RELEASED BY AMP INCORPO RA TE D. FOR ALL PUBLICATION RIGHTS , 19 LOC RE SE R VE D . DI ST G REVISIONS 50 L TR DESCRIPTION REV D 222.25 [8.75] SHOWS PER DATE 0G3A-027Q-01 MINIMUM 2 APRO' 1 D R A WI N G

Contextual Info: THIS DRAWING IS C O P Y R IG H T U N P U B L IS H E D . 19 RELEASED BY AMP INCORPO RA TE D. FOR ALL PUBLICATION RIGHTS , 19 LOC RE SE R VE D . REV IS IO NS DI ST G 50 L TR DESCRIPTION RE V D PE R DATE 0G3A-027Q-01 2 APRO' 1 D R A WI N G 2 FOR S I M P L I C I T Y ,

Contextual Info: FSYC9055D, FSYC9055R Semiconductor Radiation Hardened, SEGR Resistant P-Channel Power MOSFETs June 1998 Features Description • 59A, -60V, ros ON = 0-027Q T he D iscrete P roducts O peration of H arris S e m icon ducto r has developed a se rie s o f R adiation H ardened M O S FE T s

Contextual Info: T O S H IB A TC55V2325FF-100J TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2,097,152 bit synchronous pipelined burst SRAM that is organized as 65,536 words by 32 bits and designed for use in a secondary cache to support MPUs which have burst

Contextual Info: 4ÛSS4SS G 0 m ti5 0 b47 H I N R PD-9.896 International @sæ]Rectifier IRF520S HEXFET Power MOSFET • • • • • • • INTERNATIONAL RECTIFIER Surface Mount Available in Tape & Reel Dynamic dv/dt Rating Repetitive Avalanche Rated 175°C Operating Temperature

Contextual Info: HM51W17800B Series 2,097,152-word x 8-bit Dynamic Random Access Memory HITACHI ADE-203-275C Z Rev. 3.0 Jul. 5, 1996 Description The Hitachi HM51W17800B is a CMOS dynamic RAM organized 2,097,152-word x 8-bit. It employs the most advanced CMOS technology for high performance and low power. The HM51W17800B offers

Contextual Info: TO S H IB A TCS5V2325FM00J TOSHIBA M O S DIG ITAL INTEGRATED CIRCUIT SILICON GATE CM OS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2,097,152 bit synchronous p ip elin ed burst SRAM that is organized as 65,536