0078B Search Results

IEC134

Abstract: TDA8772 OAC 5J
Contextual Info: N AP C/ PHI LIP S SEMICONJ b3E J • tbSS'W-l 0078b 1b bil * S I C 3 P h ilip s S e m ico n d u cto rs V ideo P rodu cts_ Prelim inary specification Triple 8-bit video digital-to-analog converter TDA8772 FEATURES APPLICATIO NS

Contextual Info: Preliminary Data Sheet September 2000 T8535A/T8536A Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes — Up to 256 time slots per frame

pin diagram of ic 7495

Abstract: T8533 T8534 T8535B T8536B T8538B
Contextual Info: Preliminary Data Sheet June 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

data sheet ic 7495

Abstract: gtx2 0135 0124C 7495 ic data sheet DATA Sheet IC 555 digital clock ckt diagram ic 7495 data sheet pin diagram of ic 7495 pin diagram of ic 7495 A Ringing Subscriber Line Interface Circuit NXP
Contextual Info: Preliminary Data Sheet May 2001 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Agere read channel

Abstract: DATA Sheet IC 555 84 PLCC pin configuration data sheet book ic 555 Ringing Subscriber Line Interface Circuit NXP T8533 T8534 T8535B T8536B T8538B
Contextual Info: Preliminary Data Sheet September 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Contextual Info: T8535B/T8536B Quad Programmable Codec Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5 V operation Per-channel programmable gains, equalization, termination impedance, and hybrid balance Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Contextual Info: MITSUBISHI MICROCOMPUTERS M37735M4BXXXFP « A " 5' s «s SO^ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DESCRIPTION •S e ria l I/O UART or clock The M37735M4BXXXFP is a single-chip microcomputer using the

pin diagram of ic 7495

Abstract: data sheet ic 7495 T8533 T8534 T8535B T8536B T8538B
Contextual Info: Preliminary Data Sheet July 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Contextual Info: Preliminary Data Sheet August 2001 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

data sheet ic 7495

Abstract: T8538 0071A 321AL
Contextual Info: Advance Data Sheet October 2000 T8538A Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes — Up to 256 time slots per frame

T8533

Abstract: T8534 T8535B T8536B T8538B
Contextual Info: Data Sheet March 2002 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

grx2

Contextual Info: T8538B Quad Programmable Codec Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.3 V operation Per-channel programmable gains, equalization, termination impedance, and hybrid balance Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

pin diagram of ic 7495

Abstract: T8533 T8534 T8535A T8536A
Contextual Info: Preliminary Data Sheet March 2001 T8535A/T8536A Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

44256 dram

Abstract: reclaimer intel date code format 28F800B3 AT29C432 GF105 GM99
Contextual Info: D Flash Data Integrator FDI User’s Guide July, 1997 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

Contextual Info: Features • ■ ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame — Supports PCM data rates of 512 kbits/s to 16.384 Mbits/s — Double-clock mode timing compatible with ISDN