00155B Search Results

Contextual Info: DS2152 PRELIMINARY DALLAS DS2152 Enhanced T1 Single Chip Transceiver se m ic o n d u c to r FEATURES PIN ASSIGNMENT • Complete DS1/ISDN-PRI transceiver functionality • Line interface can handle both long and short haul trunks • 32-bit or 128-bit crystal-less jitter attenuator

KU 490-R

Abstract: ramdac ATT20C409-17M68 att20c409-17 ATT20C409 3C8 Ferrite Material
Contextual Info: Ddts Sheet June 1995 1 JCTbtüT ä A IS l Microelectronics ATT20C409: 16-Bit Interface RAMDAC Dual Clock Synthesizers PrecisionDAC Technology Features Description • 170/135 MHz speed grades — 170 MHz 2:1 multiplex 8-bit pseudocolor — 73 MHz true-color operation

Contextual Info: 8M 1M x 8 Flash Memory • High-Density Symmetrically Blocked Architecture - Sixteen 64K Blocks • Extended Cycling Capability - 100,000 Block Erase Cycles - 1.6 Million Block Erase Cycles per Chip • Automated Byte Write and Block Erase - Command User Interface

CY7C470

Abstract: CY7C472 CY7C474 pfr 4fi
Contextual Info: W CYPRESS CY7C470 CY7C472 CY7C474 8K x 9 FIFO, 16K x 9 FIFO, 32K x 9 FIFO with Programmable Flags Features Functional Description • 8K x 9 16K x 9, and 32K x 9 FIFO buffer memory • Asynchronous read/write • High-speed 333-M H z read/write independent of depth/width

BT35F

Contextual Info: Panasonic For Information Equipment MN5523A Low Power CPU Controller and I/O Peripheral LSI for Compact PC/AT Computers • Overview The MN5523A is a chip that supports CPU directly, and I/O peripherals. It is designed for use in pen-based personal digi­

Contextual Info: Diode array, high-speed switching, leaded DAN213 DAP213 Dimensions Units : mm In these single packages, there are two diodes as shown in the circuit diagrams. DAN213, DAP213 (ATVTV2) Features • available in ATV TV2 package • suitable for automatic mounting on

476A diode

Abstract: RAMDAC rs170 Ferrite 3c6 laptop screen connector pins ATT20C47XA
Contextual Info: Data Sheet June 1995 * A T 8 T ^ = j r Microelectronics ATT20C497 CMOS RAMDAC F e a tu re s Application Differences From the ATT20C478A/477A/476A/475A • Similar functionality and footprint to ATT20C478A/ 477A/476A/475A ■ 110/80/50 MHz operation ■ Powers down to 3 mA typical while retaining color

Zl13

Abstract: ZL12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140 C1308 wj 75
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex­

irfpc30

Contextual Info: International k Rectifier 4Û554S2 HEXFET® Power MOSFET INTERNATIONAL RECTIFIER 00155fei2 PD-9.596A IINR 3?S IRFPC30 Dynamic dv/dt Rating Repetitive Avalanche Rated Isolated Central Mounting Hole Fast Switching Ease of Paralleling Simple Drive Requirements

VTB1012

Abstract: VTB1013
Contextual Info: V T B 1 0 1 2 , 1013 VTB Process Photodiodes P A C K A G E DIMENSIONS inch mm PRODUCT DESCRIPTION CASE 17 A B S O LU T E MAXIMUM RATINGS Storage Tem perature: - 4 0 ° C t o 110°C Operating Temperature: - 4 0 ° C t o 1 10°C ELECTRO-OPTICAL CHARACTERISTICS @ 25°C

55B0

Contextual Info: 8M 1M X 8 Flash Memory • High-Density Symmetrically Blocked Architecture - Sixteen 64K Blocks • Extended Cycling Capability - 100,000 Block Erase Cycles - 1.6 Million Block Erase Cycles per Chip • Automated Byte Write and Block Erase - Command User Interface

ks 4290 industrial controller

Abstract: AKA NF 028 ATT2C12 ATT ORCA fpga ATT2C08 ATT2C15 52833 trw 2015 ptc ei 8n CODE PJ 62-00
Contextual Info: Preliminary Data Sheet January 1995 AT&T Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features • High density: 3,500 to 26,000 usable gates ■ High I/O: up to 384 usable I/O ■ High-performance 0.5 (xm CMOS technology

74fct651

Abstract: VLN 2003
Contextual Info: FAST CMOS OCTAL TRANSCEIVER/ REGISTERS 3-STATE In te g ra te d D evice T echnology, Inc. FEATURES: IDT54/74FCT648/2648/651 /2651 T/AT/CT consist of a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the