0013S Search Results

Contextual Info: ÛEC P L E SS EY S E MI C ON D S 43E if 37bâ52E 0013S01 ô •PLSB GEC PLESSEY ¡SEMIC ONDUCTORS I SL6270 GAIN CONTROLLED MICROPHONE PREAMPLIFIER/VOGAD The SL6270 is a silicon integrated circuit combining the functions of audio amplifier and voice operated gain

M74LS174P

Abstract: 20-PIN 251C
Contextual Info: MITSUBISHI LSTTLs M 74LS174P LOPS W IT H RESET HEX D -l DESCRIPTION The M 7 4L S 17 4P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 6 D -type edge-triggered flip -flo p circuits w ith common clock input T and direct reset input R D as well

M74LS240P

Abstract: la 7610 d 667c
Contextual Info: M ITSUBISHI L S T T L s M 74LS240P OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUTS INVERTED DESCRIPTION The M 74LS240P PIN CONFIGURATION (TOP VIEW) is a s e m ic o n d u c to r integrated c irc u it a n d c o m m o n o u tp u t c o n tro l in p u t f o r all 4 d iscrete c irc u its .

m74LS164p

Abstract: CRB 400P IC dsi 20-PIN RD 15 mitsubishi
Contextual Info: MITSUBISHI LSTTLs M74LS164P 8 -B IT SER IA L-IN PARALLEL-OUT S H IFT REGISTER DESCRIPTION The M 74LS 164P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing an 8 -b it serial input-serial/parallel ou tp ut shift register fu nction w ith direct reset input.

semiconductor w5c

Abstract: 20-PIN 251C M74LS395AP
Contextual Info: MITSUBISHI LSTTLs M74LS395AP 4 -B IT CASCADABLE S H IFT REG ISTER W IT H 3-S TA TE O UTPUT DESCRIPTION T h e M 7 4 L S 3 9 5 A P is a s em ico n d u c to r in teg ra te d c irc u it PIN CONFIGURATION TOP VIEW co n ta in in g a 3-state o u tp u t 4 -b it s e rial/p a ralle l in p u t-s e ria l/

M74LS156P

Abstract: 20-PIN M74LS155P
Contextual Info: MITSUBISHI LSTTLs M74LS156P DUAL 2 -B IT BINARY TO 4-LINE DECODER/DEMULTIPLEXER W ITH OPEN COLLECTOR OUTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74L S 15 6P is containing tw o a semiconductor integrated circuit 2-bit binary to 4-line decoders/dem ulti­

M74LS136P

Abstract: 20-PIN MITSUBISHI ELECTRIC SEMICONDUCTOR
Contextual Info: MITSUBISHI LSTTLs M 74LS136P QUADRUPLE 2 -IN P U T EXC LU SIVE OR GATES W IT H OPEN COLLECTOR O UTPU TS DESCRIPTION The M 74LS 136P containing 4 is a semiconductor integrated circuit dual-input exclusive-OR gates w ith PIN CONFIGURATION TOP VIEW open collector output.

20-PIN

Abstract: 50J2 M74LS386P
Contextual Info: MITSUBISHI LSTTLs M74LS386P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATE DESCRIPTION The M 7 4 L S 3 8 6 P is a semiconductor circuit containing four integral circuits configured into dual input exclusive OR gates. FEATURES • Capable o f withstanding high input voltages V , ^ 1 5 V

M74LS640-1P

Abstract: 20P4 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS640-1P OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74L S 64 0-1P is a semiconductor integrated circuit containing 8 bus transmitters/receivers w ith inverted ou t­ puts. DATA

TLC2201 application

Abstract: tlc221 TLC2201 LHi 807 TLC2201CP TLC2201A TLC2201ACD TLC2201ACP TLC2201B TLC2201BCD
Contextual Info: TLC2201, TLC2201A, TLC2201B, TLC2201Y Advanced LinCMOS LOW-NOISE PRECISION OPERATIONAL AMPLIFIERS SLQS021A - NOVEMBER 1988 - REVISED AUGUST 1994 TLC2201B Is 100% Tested for Noise: 30 nV/VHz Max at f = 10 Hz 12 nV/VHz Max at f = 1 kHz Low Input Offset Voltage. . . 200 pV Max

BCD-TO-7-SEGMENT DECODER

Abstract: m74ls248p M74LS247P M74LS48P m74ls48 M74LS47P
Contextual Info: MITSUBISHI LSTTLs M74LS248P B C D -TO -7 -SEGM ENT D EC O D ER /D R IVER A C TIV E -H IG H O U TP U T DESCRIPTION The M 7 4L S 24 8P is a semiconductor integrated circuit pro­ vided w ith a BCD-to-7-segment decoder/driver function and 2kohm (typ ) pull-up resistor outputs.

M74LS138P

Abstract: M74LS137P 20-PIN demultiplexer containing latch 1329T
Contextual Info: MITSUBISHI LSTTLs M74LS137P 3-LINE-TO -8-LINE DECODER/DEMULTIPLEXER W ITH ADDRESS LATCH DESCRIPTION The M 7 4L S 13 7P is a semiconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW taining a 3-line-to-8-line decoder/m ultiplexer function w ith address latch.

20-PIN

Abstract: M74LS670P
Contextual Info: MITSUBISHI LSTTLs M74LS670P 4 -B Y -4 REGISTER FILE W ITH 3-STATE OUTPUTS DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS670P is a semiconductor integrated circuit containing a 4 word x 4 bit register file circuit with 3-state outputs. i Di — [7 16] V cc

20-PIN

Abstract: M74LS37P
Contextual Info: MITSUBISHI LSTTLs M 74LS 37P Q U A D RU PLE 2-IN P U T P O S IT IV E NAND B U FFER DESCRIPTION The M 74LS 37P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing four 2-in p u t positive N A N D and negative NOR buffer gates. FEATURES

M74LS684P

Abstract: 8BIT MAGNITUDE COMPARATOR M74LS682P M74LS683P M74LS685P M74LS688P M74LS689P
Contextual Info: MITSUBISHI LSTTLs ^ M 74LS684P S -B IT M A G N ITU DE COMPARATOR DESCRIPTION T h e M 7 4 L S 6 8 4 P is a s em ico n d u c to r in teg rated c irc u it c o n ­ PIN CONFIGURATION TOP VIEW ta in in g tw o 8 -b it w o rd s c o m p a ra to r fu n ctio n s .

M74LS247P

Abstract: 7 segment 4" LT display M74LS47P 4 digits 7-segment led display display 7 segment smd 4 digits 7-segment display cl BCD-TO-7-SEGMENT DECODER 4 digits 7-segment led display cl BCD-TO-7-SEGMENT 7 segment 4 LT display
Contextual Info: MITSUBISHI LSTTLs M74LS247P B C D -TO -7-S EG M E N T D E C O D E R /D R IV E R A C T IV E -L O W O U TP U T DESCRIPTION The M74LS247P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) provided with BCD-to-7-segment decoder/driver function

M74LS377P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 7 4 L S 3 7 7 P OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP W ITH ENABLE DESCRIPTION The M 7 4L S 37 7P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 8 D -type positive edge-triggered flip -flo p circuits

20-PIN

Abstract: M74LS298P M74LS298
Contextual Info: MITSUBISHI LS TT Ls M 74LS298P QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE DESCRIPTION The M74LS298P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW which containing fo u r 2-line to 1-line m ultiplexers provided w ith a tem porary storage circu it w ith common selection

mitsubishi inverter schematic

Abstract: mitsubishi inverter air conditioning M74LS19P M74ls14p 20-PIN 74LS14P
Contextual Info: MITSUBISHI LSTTLs M74LS19P H EX SCH M ITT TRIGGER INVERTER DESCRIPTION T h e M 7 4 L S 1 9 P is a s em ico n d u c to r in teg rated c irc u it c o n ­ ta in in g 6 s c h m itt trigg er in ve rte r circuits. FEATURES • S u ita b le fo r w a v e fo rm shaping applications

M74LS166AP

Abstract: 50J2 M74LS166P 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS166AP 8 -B IT SH IFT REGISTER DESCRIPTION The M 7 4L S 16 6A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing an 8-bit serial/parallel input — serial ou tp u t shift register function. S E R IA L DATA

mitsubishi cab

Abstract: M74LS241P M74LS243P 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS243P QUADRUPLE BUS TRANSCEIVER WITH 3-STATE OUTPUT NONINVERTED DESCRIPTION The M 74L S 24 3P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit containing 4 bus transmitters/receivers w ith 3-state non­ inverted outputs.

M74LS92P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS92P DIVIDE-BY-TW ELVE COUNTER DESCRIPTION The M74LS92P is a semiconductor integrated circuit containing an asynchronous divide-by-twelve counter func­ tion w ith direct reset inputs. FEATURES • • • • Direct reset input provided

m74ls194ap

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS194AP 4 -B IT B ID IR E C TIO N A L U N IV ER SA L S H IF T REG ISTER W IT H RESET DESCRIPTION The M 7 4L S 19 4A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW w ith a 4-b it bidirectional serial/parallel input-serial/parallel

50J2

Abstract: LS290 LS90 M74LS490P
Contextual Info: MITSUBISHI LSTTLs M74LS490P DUAL 4 -B IT DECADE COUNTER DESCRIPTION The M74LS490P is a semiconductor integrated circuit containing a dual circuit asynchronous decade counter with direct reset input and direct 9-set input. FEATURES • Two integral circuits the functional equivalent of LS90