000371B Search Results

Contextual Info: EL7104C/EL7114C Features G eneral D escription • Industry standard driver replacement • Improved response times • Matched rise and fall times • Reduced clock skew • Low output impedance • Low input capacitance • High noise immunity • Improved clocking rate

Contextual Info: ADS-944 B d A T E L 14-Bit, 5MHz Sampling A/D Converters IN N O V A T IO N a n d E X C E L L E N C E FEATURES • • • • • • • • • 14-Bit resolution 5MHz minimum sampling rate No missing codes over full military temperature range Edge-triggered, no pipeline delay

NTE2000

Abstract: NTE2001
Contextual Info: LINEAR INTEGRATED CIRCUITS T03P, See Diag. 59c NTE1942 5-Lead T0220, See Diag. 205 Positive Voltage Regulator, Adjustable NTE1960 NTE1962, T0220, See Diag. 560c NTE1964, NTE1966, NTE1968, NTE1970, NTE1972, NTE1974, NTE1976, Positive Voltage Regulator, Isolated Tab

Contextual Info: GM7 1 C4 1 0 0 B/BL G oldStar 4,194,304 WORDS x l BIT CMOS DYNAMIC RAM GOLDSTAR ELECTRON CO., LTD. Description Features The GM71C4100B/BL is the new generation dy­ nam ic RAM organized 4 ,1 9 4 ,3 0 4 x 1 Bit. GM71C4100B/BL has realized higher density, higher performance and various functions by

Contextual Info: IBM11D1360Q IBM11E1360Q IBM11D2360Q IBM11E2360Q 1M/2M x 36 DRAM Module Features • 72-Pin Single-In-Line Memory Module • Performance: -60 -70 : W c ; RAS Access Time 60ns 70ns I tcAC i CAS Access Time 15ns 20ns 30ns 35ns j Iaa !Access Time From Address

89c31

Abstract: MHS 80C31 80C31 80C51 80C51F T016 80C31 instruction set MHS-C51 how to program for 8051 external memory 80c31a
Contextual Info: October 1992 80C31/80C51 DATA SHEET CMOS SINGLE-CHIP 8 BIT MICROCONTROLLER 80C31/B0CS1-L : 0 TO 6 MHz WTTH 2.7 V < Vcc < 6 V 80C51F : 80C51 WITH PROTECTED ROM 80C31/80C51 :0 TO 12 MHz 80C31/80C51-1 : 0 T 0 16 MHz 80C31-S/80C51-S : 0 TO 20 MHz FEATURES BOOLEAN PROCESSOR

STM-1 Physical interface PHY

Abstract: TCA240 341fh rca 645 PM4341A PM6341 PM7344 PM7345 PUB54016 E1 HDB3
Contextual Info: PMC-Sierra, Inc. • " ISSUE 5 PM7344 S/UNI-MPH SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE FEA TU RES • Single chip quad ATM User Network Interface operating at 1.544 Mbit/s or 2.048 Mbit/s. • Implements the ATM Forum User Network Interface Specification V3.1 for DS1

LT010MC

Abstract: LT010 DGG37 DGG371S
Contextual Info: SHARP ELEK/ HELEC DIV 17E D • aiöQT'ia DGG371S S ■ LT010MC/MD/MF :x m Features • Wavelength: 810nm • Single transverse mode Applications • Measurement instruments • Short-distance communications • Information Processing equipment Absolute Maximum Ratings

V53C664H

Abstract: mosel MT
Contextual Info: MOSEL VITELIC V53C664H 6 4 K x 16 B IT F A S T P A G E M O D E B Y TE W RITE CM OS D YN A M IC R A M V53C664H 50 55 60 Max. RAS Access Time, tRAC 50 ns 55 ns 60 ns Max. Column Address Access Time, (tCAA) 26 ns 28 ns 30 ns Min. Fast Page Mode Cycle Time, (tpc)

BU4052BF

Abstract: BU4052 BU4052B
Contextual Info: MOE D ROHM CO LT» Q IC /S tandard ICs 7626^ 0003713 b Q R H M BU4052B/BU4052BF ’ -!— B I S <4 0 2 5 2 ! B 4 7 = S-/-/Z f a 7 i l / 4ch T±n?-?J['?7'\s<7V'/: r ’? l'?70l''7'yDual 4-C hannel Analog Multiplexer/Demultiplexer

schematic diagram for ac power line voltage condi

Abstract: schematic diagram for power line ac voltage condi L600P transformer less power supply 6v output main transformer secondary 6V 200mA specification Three-terminal Off-line PWM Switch DDD3714 LX1570 LX1571 voltage regulator PWM 1995 transconductance sink
Contextual Info: P M I C K O T h e I n f i n i t e P E I. E C T K O o w e r o f I N a t e n P h ase M n n o v a t i o n t o d u lated P AC S ynchronous S r e l i m i n a r y DESCRIPTION The LX1570/71 series of controller ICs are designed to provide all control functions in

Contextual Info: VITESSE VS8061/8062 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset Features • Serial Data Rate up to 2.5 Gb/s • 16-bit Wide ECL 100K Compatible Parallel Data Interface • Differential High Speed Data Outputs • Differential or Single-ended High Speed Data