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    DSASW0010764.pdf

    • PMC-Sierra
    • RM7000C Released 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 16 Kbytes instruction, 16 Kbytes data, 256 Kbytes on-chip secondary. ยท Per line cache locking in primaries
    • Original
    • Part pricing, stock, data attributes from Findchips.com

    DSASW0010764.pdf preview Download Datasheet

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    16 bit single cycle mips GT-6424 gt-64240 GT-96122 gt64240 l2 cache controller mips MV64340 RM5271 RM7000 RM7000A RM7000B RM7000C
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