ZZ28 Search Results

Contextual Info: CY24272 Rambus XDR Clock Generator with Zero SDA Hold Time Rambus‚ XDR™ Clock Generator with Zero SDA Hold Time Features • Table 1. Device Comparison Meets Rambus Extended Data Rate XDR™ clocking requirements ■ 25 ps typical cycle-to-cycle jitter

CY28400OXC-2

Abstract: CY28400OXC-2T CY28400ZXC-2 CK409 CK410 CY28400-2
Contextual Info: CY28400-2 100 MHz Differential Buffer for PCI Express and SATA Features • SMBus Block/Byte/Word Read and Write support • 3.3V operation • CK409 and CK410 companion buffer • PLL Bypass-configurable • Four differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and

CY2SSTV855

Abstract: CY2SSTV855ZC CY2SSTV855ZCT CY2SSTV855ZI CY2SSTV855ZIT
Contextual Info: CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description • Phase-locked loop PLL clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to

Contextual Info: W40S11-02 SDRAM Buffer - 2 DIMM Mobile Features Key Specifications • Ten skew-controlled CMOS outputs (SDRAM0:9) Supply Voltages: . VDD = 3.3V±5% • Supports two SDRAM DIMMs Operating Temperature:. 0°C to +70°C

CK409

Abstract: CK410 CY28400-2 CY28400OXC-2 CY28400OXC-2T CY28400ZXC-2
Contextual Info: CY28400-2 100 MHz Differential Buffer for PCI Express and SATA Features • SMBus Block/Byte/Word Read and Write support • 3.3V operation • CK409 and CK410 companion buffer • PLL Bypass-configurable • Four differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and

1990- 2335 optocoupler

Abstract: philips 3139 147 tv tuner TDA6101Q equivalent TDA3827 tda6100 ofw g 3201 ica v94 display OFW G 3352 BB515 pj 2309 smd diode
Contextual Info: Philips S em iconductors S em ico n d u cto rs fo r Television and V id eo S ystem s Contents PART A page SELECTION GUIDE Functional index 5 Numerical index 17 Maintainance list 27 GENERAL Quality 31 Pro Electron type numbering system for Discrete Semiconductors

CY2SSTV855ZXCT

Abstract: CY2SSTV855 CY2SSTV855ZC CY2SSTV855ZCT CY2SSTV855ZI CY2SSTV855ZIT CY2SSTV855ZXI CY2SSTV855ZXIT
Contextual Info: CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description • Phase-locked loop PLL clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to

DA 106962

Abstract: IMIC9531CYT CYI9531 CYI9531OXCT C9531 IMIC9531CT IMIC9531CY CPU TSSOP IA2 dmg cpu 114504
Contextual Info: C9531 PCIX I/O System Clock Generator with EMI Control Features Features Table 1. Test Mode Logic Table[1] • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter Input Pins OE S1 Output Pins S0 CLK REF • Input clock frequency of 25 MHz to 33 MHz

CY2SSTV855ZXCT

Abstract: CY2SSTV855ZCT CY2SSTV855ZI CY2SSTV855ZIT CY2SSTV855ZXI CY2SSTV855ZXIT CY2SSTV855 CY2SSTV855ZC
Contextual Info: CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description • Phase-locked loop PLL clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to

Contextual Info: CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description • Phase-locked loop PLL clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to

Contextual Info: THIS SPEC IS OBSOLETE Spec No.: 001-42225 Spec Title: CY28517 PCI EXPRESS CLOCK GENERATOR Sunset Owner: Christopher Martin CXQ Replaced by: NONE CY28517 PCI Express Clock Generator Features • Selectable, Triangle, and Lexmark profiles ■ Four 100 MHz differential clocks

Contextual Info: CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description • Phase-locked loop PLL clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to

CYI9531

Abstract: CYI9531OXCT IMIC9531CY IMIC9531CYT C9531 IMIC9531CT
Contextual Info: C9531 PCIX I/O System Clock Generator with EMI Control Features Table 1. Test Mode Logic Table[1] Features Input Pins • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter OE Output Pins S1 S0 CLK REF • Input clock frequency of 25 MHz to 33 MHz

IMIC9531CYT

Abstract: ZZ28
Contextual Info: C9531 PCIX I/O System Clock Generator with EMI Control Features Table 1. Test Mode Logic Table[1] Features Input Pins • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter OE Output Pins S1 S0 CLK REF • Input clock frequency of 25 MHz to 33 MHz

CY24271

Abstract: CY24272 CY24272ZXC CY24272ZXCT
Contextual Info: CY24272 Rambus XDR Clock Generator with Zero SDA Hold Time Features • Table 1. Device Comparison Meets Rambus® Extended Data Rate XDR™ clocking requirements ■ 25 ps typical cycle-to-cycle jitter ❐ –135 dBc/Hz typical phase noise at 20 MHz offset

vl86c020

Contextual Info: V L S I TECHNOLOGY INC 1ÔE D • 1300347 0005016 T ■ Ji'i«-Í7-Í2. VLSI T ech n o lo g y , in c . VL86C020 32-BIT RISC MICROPROCESSOR WITH CACHE MEMORY FEATURES DESCRIPTION • On-chip 4 Kbyte 1K x 32 bits cache memory The VL86C020 Acorn RISC Machine

Contextual Info: CY28400-2 100 MHz Differential Buffer for PCI Express and SATA Features • SMBus Block/Byte/Word Read and Write support • 3.3V operation • CK409 and CK410 companion buffer • PLL Bypass-configurable • Four differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and

CY2SSTV855ZXCT

Abstract: CY2SSTV855 CY2SSTV855ZC CY2SSTV855ZCT CY2SSTV855ZI CY2SSTV855ZIT CY2SSTV855ZXI CY2SSTV855ZXIT
Contextual Info: CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description • Phase-locked loop PLL clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to

CY28400-2

Abstract: CK409 CK410 CY28400OXC-2 CY28400OXC-2T CY28400ZXC-2
Contextual Info: CY28400-2 100-MHz Differential Buffer for PCI Express and SATA Features • SMBus Block/Byte/Word Read and Write support • 3.3V operation • CK409 and CK410 companion buffer • PLL Bypass-configurable • Four differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and

CY2SSTV855ZXCT

Abstract: CY2SSTV855 CY2SSTV855ZC CY2SSTV855ZCT CY2SSTV855ZI CY2SSTV855ZIT CY2SSTV855ZXI CY2SSTV855ZXIT
Contextual Info: CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description • Phase-locked loop PLL clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to

Contextual Info: CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description • Phase-locked loop PLL clock distribution for Double Data Rate Synchronous DRAM applications • 1:5 differential outputs • External feedback pins (FBINT, FBINC) are used to

27m21

Abstract: CY28517 VSS100 DB-25M RoHS VSS-100
Contextual Info: CY28517 PCI Express Clock Generator Features • Four 100 MHz differential clocks ■ 48 MHz clock ■ Two 25 MHz clocks ■ 27 MHz Reference Clock ■ OE control per clock output ■ ■ Selectable, Triangle, and Lexmark profiles ■ SMbus support with readback capabilities

CK409

Abstract: CK410 CY28400-2 CY28400OXC-2 CY28400OXC-2T CY28400ZXC-2
Contextual Info: CY28400-2 100-MHz Differential Buffer for PCI Express and SATA Features • SMBus Block/Byte/Word Read and Write support • 3.3V operation • CK409 and CK410 companion buffer • PLL Bypass-configurable • Four differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and

DA 106962

Abstract: C9531 IMIC9531CT IMIC9531CY IMIC9531CYT CYI9531
Contextual Info: C9531 PCIX I/O System Clock Generator with EMI Control Features Features Table 1. Test Mode Logic Table[1] • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter Input Pins OE S1 Output Pins S0 CLK REF • Input clock frequency of 25 MHz to 33 MHz