Z8000 DMA Search Results

Z8010

Abstract: Z8002 Z8003 Z8090 86dec z8000 microprocessor zilog Z8000 Z8001 Z8000A z8000cpu
Contextual Info: Oi Z8000 Z8000 CPU User's Reference M anual Z8000 CPU User's Reference M anual •t : i T i l ■7-nA / t Zilog Prentice-Hall, Inc., Englewood Cliffs, New Jersey 07632 L ib r a r y o f C o n g ress C a ta lo g in g in P ublication Data M ain entry u nder title:

Z8000

Abstract: z80a-PIO IN SDLC PROTOCOL USING SCC WITH Z8000 IN SDLC PROTOCOL Z8002 Z8002-CPU Z8030 IN SDLC program z8000 development module SDLC
Contextual Info: APPLICATION NOTE 1 USING SCC WITH Z8000 IN SDLC PROTOCOL 11 INTRODUCTION This application note describes the use of the Z8030 Serial Communications Controller SCC with the Z8000 CPU to implement a communications controller in a Synchronous Data Link Control (SDLC) mode of

Zilog Z320

Abstract: z8000 microprocessor zilog Z08016 Z08038 Z08581 Z08060 Z80320 Z80000 Microprocessor z8000 Z8581
Contextual Info: ^ 3LG b 1 Zilog Z8000 Family Architecture A High-Performance 16-Bit Architecture With 32-Bit Migration Z8000 16 Bit C P U ’s Z80,000™ 32 Bit CPU'S In the office, in the factory, even in the home-every day the numberof people using microprocessors grows. And every

c828 transistor datasheet

Abstract: C828 transistor transistor c828 c828 Z80A-CTC a684 transistor C838 transistor c828 datasheet z80a-PIO C880 transistor
Contextual Info: APPLICATION NOTE 9 SCC IN BINARY SYNCHRONOUS COMMUNICATIONS 9 INTRODUCTION Zilog’s Z8030 Z-SCC Serial Communications Controller is one of a family of components that are Z-BUS compatible with the Z8000 CPU. Combined with a Z8000 CPU or other existing 8- or 16-bit CPUs with nonmultiplexed buses

reflectometer

Abstract: BIT1502
Contextual Info: Am7990 Local Area Network Controller for Ethernet LANCE IN DEVELOPMENT DISTINCTIVE CHARACTERISTICS GEN ERA L DESCRIPTION • Compatible with Ethernet specifications • Easily interfaced to 8086, 68000, Z8000, LSI-II microprocessors • On-board DMA and buffer management

AM22V10

Abstract: MS 1117
Contextual Info: Am7990* Am7990* Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS • • • • Ethernet and IEEE 802.3 compatible Easily interfaced to 8086, 68000, Z8000, LSI-II micro­ processors On-board DMA and buffer management, 48 byte FIFO

z8000cpu

Abstract: Z8000 Z8001 Z8002 Z8010 Z8000A CPU Zilog z8000 manual rs001s
Contextual Info: Z8000 CPU Technical Manual » 7 ^ 1 • 7 il • 7 -i1 ZilOQ fable of Contents 1.1 1.2 1.3 Introduction . 1-1 G eneral O rg a n iz a tio n . . . . 1-1

AM22V10

Abstract: E5ES E5ES MODE PAL16L8 programming algorithm dali power supply circuit diagram CSRQ
Contextual Info: Am7990* Am7990* Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS Ethernet and IEEE 802.3 compatible Easily interfaced to 8086, 68000, Z8000, LSI-II micro­ processors On-board DMA and buffer management, 48 byte FIFO 24-bit wide linear addressing (Bus Master Mode)

am8160

Abstract: str f 6167 Amz8127 74LS240 MC68000 Z8000 Z80A Z80B 50lh 71p3ns
Contextual Info: Am8163/Am8167 Am 8163/Am 8167 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

Z8015

Contextual Info: Z8015 Z8000 PNNU Paged Memory Management Unit Product Specification A p r il 1985 • PMMU architecture supports m ultiprogram m ing systems and virtual memory implementations. ■ Dynamic page relocation makes software addresses independent of physical memory addresses.

Contextual Info: Z8031 Z8000 Z-ÄSCC Asynchronous Serial Communications Controller Product Specification Zilog April 1985 Features • Two independent, 0 to 1M bit/second, fullduplex channels, each with a separate crystal oscillator and baud rate generator. ■ Programmable for NRZ, NAZI, or FM data

AM7990

Contextual Info: Am7990 Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS • • • • • Compatible with Ethernet and IEEE-802.3 10Base5 Type A, and 10Base2 Type B, "C heapernet") Easily interfaced to 8086, 68000, Z8000*, LSI-II* microprocessors

nonseg

Contextual Info: Z8001 / Z8002® Military Z8000® CPU Central Processing Unit Military Electrical Specification 17 :1 M llO y September 1988 FEATURES • Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers ■ Directly addresses 8

am7990

Abstract: time domain reflectometer AM7990DC
Contextual Info: Am7990 Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS Compatible with Ethernet and IEEE-802.3 Rev D (10 Base 5 Type A, and 10 Base 2 Type B, "Cheapernet") Easily interfaced to 8086, 68000, Z8000, LSI-II micro­ processors On-board DMA and buffer management, 48 byte FIFO

AMZ8000

Abstract: DF000380 AmZ8001/AmZ8002
Contextual Info: Am8127 Am8127 Am Z8000 C lo c k G e n e ra to r DISTINCTIVE CHARACTERISTICS High-drlve high-level clock output Special output provides clock signal matched to re­ quirements of AmZ8000* CPU 4MHz and some 6MHz applications , M MU and DMA devices. Synchronized WAIT state and time-out controls

str f 6167

Abstract: amz8127 str 6167 supi 3 ls z80b Am8001 AM8163 IC HS 8167 z80 multibus 74LS240
Contextual Info: Am8163/Am8167 A m 8 1 6 3 /A m 8 1 6 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

z08030

Abstract: TDA 2020 Application Z0803006CME Z0803004CMB z0803006 M/TDA 2016 Z08030-04CMB TDA 2020 z080300
Contextual Info: | ¿ illO y Z8030 Military Z8000 Z-SCC Serial Communications Controller Military Electrical Specification D ecem ber 1989 FEATURES • Two independent, 0 to 1.5M bit/second, full-duplex channels, each with a separate crystal oscillator, baud rate generator, and Digital Phase- Locked Loop for clock

z0800206

Abstract: Z0800106 Z0800110 Z08002 Z0800 Z0800204CMB zilog z8001 1065D Z08002-06CMB TDA 2025
Contextual Info: ZIL06 INC 17E D • ^ 3 4 0 4 3 0013b77 T Z8001 / Z 80023 Military Z8000® CPU Central Processing Unit 17 '! - ^ Military Electrical Specification o -7 September 1988 FEATURES ■ Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers

Z160 gpu

Abstract: Z08001 zilog z160 zilog z16 Z160 z0800 ba1515 5 R 107 hj 4094 AD0-AD15
Contextual Info: v Zilog i -pìì^ifiyi., i3g s««“ î!5ïg^ggs»»^: Product Specification Z160 CPU Central Processing Unit October 1988 FEATURES • Fully software compatible member of the Z8000 architecture. ■ Instruction set more powerful than many minicomputers

Z-SCC

Abstract: Z8030A Z8030 PS SL441 Z8030CS CRC-16 RR15 WR10 Z8000 Z8030
Contextual Info: Z8030 Z8000 Z-SCC Serial Communications Controller Product Specification Zilog April 1985 Features synchronous characters and CRC generation and checking with CRC-16 or CRC-CCITT preset to either Is or Os. • Two independent, 0 to 1.5M bit/second, fullduplex channels, each with a separate crystal

Z8010

Abstract: z8010cs Z8000 Z8001 Z8003 Z8010B Z8010-MMU Z8010APS AD10 zilog z8001
Contextual Info: Z 8010 Z8000 MMU Memory Management Unit 17 "I Ä „ “ « O y Product Specification A pril 1985 • Dynamic segm ent relocation m akes software addresses independent of physical memory addresses. ■ Sophisticated m em ory-m anagem ent features include access validation that protects

Z8030ACS

Abstract: Z8030APS Z8030A IN SDLC PROTOCOL USING SCC WITH Z8000 IN SDLC PROTOCOL CRC-16 Z8000 Z8030 z-scc Z8030 PS
Contextual Info: Z8030 Z8000 Z-SCC Serial Communications Controller Product Specification Zilog A pril 1985 • Two in dependent, 0 to 1.5M bit/second, fullduplex channels, eac h with a separate crystal oscillator, b a u d rate generator, a n d Digital Phase-L ocked Loop for clock recovery.

Contextual Info: Z8031 Z8000 Z-ASCC Asynchronous Serial Communications Controller •7 j I ¿ ■ l lO C J Product Specification April 1985 ■ Two independent, 0 to 1M bit/second, fullduplex channels, each with a separate crystal oscillator and baud rate generator. ■ Programmable for NRZ, NRZI, or FM data

Z8015

Abstract: Z8003 Z8000 2081 0000 02
Contextual Info: Z IL O G IN C 72 Ï> Ë T ifl4 0 4 3 D D 0 S b fl7 fa " 'f f T -5 2 -3 3-25 Z8015 Z8000 PMMlf Paged Memory Management Unit Product Specification April 1985 N FEATURES • PMMU architecture supports multiprogramming systems and virtual memory implementations.