Z8000 DMA Search Results

Zilog Z320

Abstract: z8000 microprocessor zilog Z08016 Z08038 Z08581 Z08060 Z80320 Z80000 Microprocessor z8000 Z8581
Contextual Info: ^ 3LG b 1 Zilog Z8000 Family Architecture A High-Performance 16-Bit Architecture With 32-Bit Migration Z8000 16 Bit C P U ’s Z80,000™ 32 Bit CPU'S In the office, in the factory, even in the home-every day the numberof people using microprocessors grows. And every

reflectometer

Abstract: BIT1502
Contextual Info: Am7990 Local Area Network Controller for Ethernet LANCE IN DEVELOPMENT DISTINCTIVE CHARACTERISTICS GEN ERA L DESCRIPTION • Compatible with Ethernet specifications • Easily interfaced to 8086, 68000, Z8000, LSI-II microprocessors • On-board DMA and buffer management

AM22V10

Abstract: MS 1117
Contextual Info: Am7990* Am7990* Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS • • • • Ethernet and IEEE 802.3 compatible Easily interfaced to 8086, 68000, Z8000, LSI-II micro­ processors On-board DMA and buffer management, 48 byte FIFO

AM22V10

Abstract: E5ES E5ES MODE PAL16L8 programming algorithm dali power supply circuit diagram CSRQ
Contextual Info: Am7990* Am7990* Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS Ethernet and IEEE 802.3 compatible Easily interfaced to 8086, 68000, Z8000, LSI-II micro­ processors On-board DMA and buffer management, 48 byte FIFO 24-bit wide linear addressing (Bus Master Mode)

am8160

Abstract: str f 6167 Amz8127 74LS240 MC68000 Z8000 Z80A Z80B 50lh 71p3ns
Contextual Info: Am8163/Am8167 Am 8163/Am 8167 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

Z8015

Contextual Info: Z8015 Z8000 PNNU Paged Memory Management Unit Product Specification A p r il 1985 • PMMU architecture supports m ultiprogram m ing systems and virtual memory implementations. ■ Dynamic page relocation makes software addresses independent of physical memory addresses.

Contextual Info: Z8031 Z8000 Z-ÄSCC Asynchronous Serial Communications Controller Product Specification Zilog April 1985 Features • Two independent, 0 to 1M bit/second, fullduplex channels, each with a separate crystal oscillator and baud rate generator. ■ Programmable for NRZ, NAZI, or FM data

AM7990

Contextual Info: Am7990 Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS • • • • • Compatible with Ethernet and IEEE-802.3 10Base5 Type A, and 10Base2 Type B, "C heapernet") Easily interfaced to 8086, 68000, Z8000*, LSI-II* microprocessors

am7990

Abstract: time domain reflectometer AM7990DC
Contextual Info: Am7990 Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS Compatible with Ethernet and IEEE-802.3 Rev D (10 Base 5 Type A, and 10 Base 2 Type B, "Cheapernet") Easily interfaced to 8086, 68000, Z8000, LSI-II micro­ processors On-board DMA and buffer management, 48 byte FIFO

AMZ8000

Abstract: DF000380 AmZ8001/AmZ8002
Contextual Info: Am8127 Am8127 Am Z8000 C lo c k G e n e ra to r DISTINCTIVE CHARACTERISTICS High-drlve high-level clock output Special output provides clock signal matched to re­ quirements of AmZ8000* CPU 4MHz and some 6MHz applications , M MU and DMA devices. Synchronized WAIT state and time-out controls

str f 6167

Abstract: amz8127 str 6167 supi 3 ls z80b Am8001 AM8163 IC HS 8167 z80 multibus 74LS240
Contextual Info: Am8163/Am8167 A m 8 1 6 3 /A m 8 1 6 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

z08030

Abstract: TDA 2020 Application Z0803006CME Z0803004CMB z0803006 M/TDA 2016 Z08030-04CMB TDA 2020 z080300
Contextual Info: | ¿ illO y Z8030 Military Z8000 Z-SCC Serial Communications Controller Military Electrical Specification D ecem ber 1989 FEATURES • Two independent, 0 to 1.5M bit/second, full-duplex channels, each with a separate crystal oscillator, baud rate generator, and Digital Phase- Locked Loop for clock

Z-SCC

Abstract: Z8030A Z8030 PS SL441 Z8030CS CRC-16 RR15 WR10 Z8000 Z8030
Contextual Info: Z8030 Z8000 Z-SCC Serial Communications Controller Product Specification Zilog April 1985 Features synchronous characters and CRC generation and checking with CRC-16 or CRC-CCITT preset to either Is or Os. • Two independent, 0 to 1.5M bit/second, fullduplex channels, each with a separate crystal

Z8030ACS

Abstract: Z8030APS Z8030A IN SDLC PROTOCOL USING SCC WITH Z8000 IN SDLC PROTOCOL CRC-16 Z8000 Z8030 z-scc Z8030 PS
Contextual Info: Z8030 Z8000 Z-SCC Serial Communications Controller Product Specification Zilog A pril 1985 • Two in dependent, 0 to 1.5M bit/second, fullduplex channels, eac h with a separate crystal oscillator, b a u d rate generator, a n d Digital Phase-L ocked Loop for clock recovery.

Z8015

Abstract: Z8003 Z8000 2081 0000 02
Contextual Info: Z IL O G IN C 72 Ï> Ë T ifl4 0 4 3 D D 0 S b fl7 fa " 'f f T -5 2 -3 3-25 Z8015 Z8000 PMMlf Paged Memory Management Unit Product Specification April 1985 N FEATURES • PMMU architecture supports multiprogramming systems and virtual memory implementations.

JD 1803

Abstract: Z8000 z80 z-cio lcd tv diagrame Z8036Z-CI0 DC20 Z8036 Z8536 Z8500 BC336
Contextual Info: MARCOM DC20 91 Zilog June 1987 DOC U M E N T C O NTROL MASTER anua Z8036 Z-CIO/Z8536 CIO Counter/Timer and Parallel I/O Unit Z8036Z-CI0 Z8536 CIO Technical Manual »7 : 1 Zilog I Z8000 is a registered trademark of Zilog, Inc. 1982, 1987 by Zilog, Inc.

Contextual Info: «*»*?ÄäHä«SSSäii{$£ai Zilog ADVANCED INFORMATION P r o d u c t S p e c if ic a t io n Z8001 / Z8002® Z8000® CPU Central Processing Unit October 1988 FEATURES • Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers

Z0803606PSC

Abstract: Z0803604CMB IC LYLE 101000 Z0803606VSC ic 4043 Z0803606LME Z8000 Z8036 crei stt
Contextual Info: <£SLO E Product S p ec ific atio n Z8036 Z8000 Z-CIO Counter/Timer and Parallel I/O Unit September 1988 Feature« G eneral DMcription Two independent 8-bit, double-buffered, bidirectional I/O ports plus a 4-bit special-purpose I/O port. I/O ports feature programmable polarity,

zilog 664

Abstract: constant time delay marking WR9 8085 Function Generators Z8000 Z8091
Contextual Info: Z8031 Z8000 Z-ASCC Asynchronous Serial Com m unications Controller •7 j I ¿ illO g Product Specification A pril 1985 ■ Two in dependent, 0 to 1M bit/second, fullduplex channels, e ach with a separate crystal oscillator an d bau d rate generator. ■ Program m able for NRZ, NRZI, or FM data

Z8015

Abstract: Z8003 Z8000 z8000 family oyle AD10 Z8001 Z8002 Z8004 A19L
Contextual Info: Z 8 0 1 5 Z8000 PNNU Paged Memory Management Unit Product Specification April 1985 • PMMU a rc h ite c tu re s u p p o rts m u ltip ro g ra m m in g system s and virtual m e m ory im plem entations. ■ D ynam ic p a g e relocation m akes software addresses

z8000 microprocessor zilog

Abstract: TDA 2020 Application zilog z8001 lc38a z8010 SNV 2020 Z3001
Contextual Info: ZILOG INC 17E D •^04043 DD11Ö71 1 ' J i P V À N C E D :ÏN E O R M A T IO N ^ r o d u ^ ^ p e c ific a tio n T . q 01. n - 0 7 Z3001 / Z8002® Z 8000C PU Central Processing Unit October 1988 FEATURES ■ Regular, easy-to-use architecture ■ Instruction set more powerful than many m inicomputers

z8000 dma

Abstract: Z8000
Contextual Info: Alphanumeric C R T Controller Chip-Set DISTINCTIVE CHARACTERISTICS 100MHz video dot rate supports high resolution CRT monitors with 132/60 or 96/66 screen formats Background or window soft-scroll capability without external MSI or software overhead User-friendly CPU interface. Compatible with 8086,

Z8000

Abstract: z8000 manual
Contextual Info: Z8030/Z8530 SCC Serial Communications Controller DISTINCTIVE CHARACTERISTICS Tw o IM.bps full duplex serial channels Each channel has independent oscillator, baud-rate generator, and PLL fo r clock recovery, dram atically reducing external com ponents. Programmable protocols

Z8000

Abstract: z8530 8086 logic diagram dc av converter Z8030 8086 interrupt structure 8086 structure interrupt structure of 8086 CRC-16 Z-636
Contextual Info: Z8030/Z8530 Serial Communications Controller DISTINCTIVE CHARACTERISTICS • Programmable Synchronous Modes - SDLC and HDLC, and SOLC loop supported with frame control, zero insertion and deletion, abort, a residue handling - CRC-16 and CCITT generators and checkers