YI11 Search Results

bfp 11A diode

Contextual Info: Si GEC PLESSEY S I M I t O N I L C T O H S P D S P 1 6 1 1 6 /A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes version October 1995 verison, DS3707 - 3.0) The PQSP16116A will multiply two complex (1 6 + 1 6 ) bit words every 50ns and can be configured to output the

AN59

Abstract: PDSP1601 PDSP16116 PDSP16116A PDSP16318 Application of dsp in sonar for m.sc i-C4H10
Contextual Info: AN59 A High Resolution FFT Processor Application Note AN59 ISSUE 2.0 July 1993 The PDSP16116A has been designed with an integral Block Floating Point system which can be used, in conjunction with other Zarlink Semiconductor PDSP parts, to process FFTs with a combination of speed and accuracy previously unobtainable. All the

Contextual Info: PDSP16116/A/MC PDSP16116/A/MC 16 By 16 Bit Complex Multiplier DS3858 - 3.0 June 2000 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The

parallel Multiplier Accumulator based on Radix-2

Abstract: DS3707 PDSP16116 PDSP16116A PDSP16318A subtractor using TTL CMOS GG144 4 bit binary full adder and subtractor 32-bit adder block diagram for barrel shifter
Contextual Info: PDSP16116 16 X 16 Bit Complex Multiplier Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications.

ALU of 4 bit adder and subtractor

Abstract: MIL-883 PDSP16116 PDSP16116A PDSP16318 logic diagram to setup adder and subtractor using
Contextual Info: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.

Contextual Info: Si GEC P L E S S E Y OCTOBER 1997 S E M I C O N D U C T O R S DS3707 - 5.3 P D S P 16 116 16X16 BIT COMPLEX MULTIPLIER Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 1 6 x1 6 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup­

FULL SUBTRACTOR using 41 MUX

Abstract: DS3707 32 bit barrel shifter circuit diagram using multi bfp mark diode YI11 MT52L1G32D4PG-107 WT:B TR
Contextual Info: MITEL PD SP16116 16 X 16 Bit Complex Multiplier SEMICONDUCTOR Supersedes O ctober 1996 version, DS3707 - 4.2 DS3707 - 5.3 O ctober 1997 The PDSP16116 contains four 16x16 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup­

BUTTERFLY DSP

Abstract: WI13 IC5-H10 dar5 AN59 PDSP1601 PDSP16116 PDSP16116A PDSP16318 BR13
Contextual Info: AN59 A High Resolution FFT Processor Application Note AN59 ISSUE 2.0 July 1993 The PDSP16116A has been designed with an integral Block Floating Point system which can be used, in conjunction with other Zarlink Semiconductor PDSP parts, to process FFTs with a combination of speed and accuracy previously unobtainable. All the

Contextual Info: PDSP16116/A OCTOBER 1996 DS3707 - 4.2 PDSP16116/A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes version October 1995 verison, DS3707 - 3.0 The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The

DS3707

Contextual Info: M ITEL PD SP16116 16 X 16 Bit Complex Multiplier SE M IC O N D U C T O R Supersedes October 1996 version, DS3707 - 4.2 DS3707 - 5.3 October 1997 The PDSP16116 contains four 1 6 x1 6 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup­

Contextual Info: • 1P 1LE S S E Y S E M IC O N D U C T O R S PDSP16112/PDSP16112A 16 x 12 BIT COMPLEX MULTIPLIER • 20M H z C om plex N um ber 16 + 16 x (12 + 12) Multiplication I Pipelined A rchitecture ■ Power Dissipation only 500m W B TT L C om patible Inputs APPLICATIONS

xlxx

Abstract: xi12 YI11 yr03
Contextual Info: P LESSEY SEMICONDUCTORS 13E D • 725 1513 OOlOObb 3 PLESSEY W Semiconductors ■ PDSP16112/PDSP16112A 16 x 12 BIT COMPLEX MULTIPLIER (SU P ER SED ES MARCH 1987 EDITION The PDSP16112/PDSP16112A w ill m ultiply a com plex (16 + 16) bit data word by a com plex (12 + 12) bit coefficient

LA1245

Abstract: sumida ift coil band pass filter 455khz 455KHZ IFT VCC 12V 34H-052-869 toko cfmq C114 C115 R208 toko ift coil
Contextual Info: Ordering number : EN737G Monolithic Linear IC LA1245 AM Electronic Tuner Overview LA1245 is a high performance IC to be used as an AM electronic tuner. It provides an automatic search-stop signal, local oscillator buffer-output, and the low level local oscillation, as well as providing all other functions required of an AM tuner.

barrel shifter block diagram

Abstract: parallel Multiplier Accumulator based on Radix-2 ALU of 4 bit adder and subtractor CD11N TTL ALU of 4 bit adder and subtractor radix-2 YIO 98 PDSP16116 PDSP16116A PDSP16318
Contextual Info: PDSP16116/A/MC MITEL 16 By 16 Bit Complex Multiplier SEM ICON D UCTOR Supersedes July 1993 version, DS3858 - 1.0 DS3858 - 2.0 O ctober 1998 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The

32 bit adder

Abstract: PDSP16116 MIL-883 PDSP16116A PDSP16318
Contextual Info: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.

YR13

Abstract: PDSP16116
Contextual Info: PDSP16116 16 X 16 Bit Complex Multiplier DS3707 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex 16116

4 bit barrel shifter circuit for left shift

Contextual Info: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.

aeg diode Si 11 n

Contextual Info: Si GEC P L E S S E Y S f M I C. O IN D ADVANCE INFORMATION L C T O R S P D S P 1 6 1 1 6 /A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes version in December 1993 Digital Video & Digital Signal Processing 1C Handbook, HB3923-1) The PDSP16116A will m ultiply tw o complex (16 + 1 6 ) bit

144 pin pga

Abstract: PDSP16116 PDSP16116A PDSP16318 diode b10
Contextual Info: PDSP16116/A/MC PDSP16116/A/MC 16 By 16 Bit Complex Multiplier Supersedes July 1993 version, DS3858 - 1.0 DS3858 - 2.0 October 1998 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The

la1245

Abstract: ALPS TEC 455kHz 270uH TOKO 34H-052-869 am tuner hand tuning sumida ift coil
Contextual Info: Ordering number : EN737G Monolithic Linear IC LA1245 AM Electronic Tuner Overview LA1245 is a high performance IC to be used as an AM electronic tuner. It provides an automatic search-stop signal, local oscillator buffer-output, and the low level local oscillation, as well as providing all other functions required of an AM tuner.

Contextual Info: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.

logic diagram to setup adder and subtractor

Abstract: YR10 FFT 1024 point implementing ALU with adder/subtractor PR11 MIL-883 PDSP16116 PDSP16116A PDSP16318 tag l9 230
Contextual Info: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.

Contextual Info: JANUARY 1990 PILE SSEY S E M IC O N D U C T O R S : P D S P 1 6 1 1 6 / 1 6 1 1 6 A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes April 1989 Edition The PDSP16116A will multiply two complex (16+16) bit words every 50ns and can be configured to output the com­

Contextual Info: DIGITAL VIDEO & DIGITAL SIGNAL PROCESSING IC Handbook GEC P L E S S E Y SEMICONDUCTORS Foreword GEC Plessey Semiconductors has substantially increased its activities in Digital Video developments since the last issue of this handbook in December 1993 . A