Y7C373 Search Results

Contextual Info: ” / C Y P R E S S C Y 7 < M UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology

Contextual Info: fax id: 6138 Y7C373Ì C'i- UltraLogic 64-Macrocell Flash CPLD • Pin compatible with the CY7C374i Features Functional Description • 64 macrocells in four logic blocks • 64 I/O pins • 5 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology

Contextual Info: fax id: 6138 CYPRESS PRELIMINARY Y7C373Ì UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram m able ISR™ Flash technology

Contextual Info: O T / OC5 /0 5 :» /» ^ R e v is io n : J u n e 24, 1996 Y7C373 rw CYPRESS UltraLogic 64-M acrocell Flash CPLC F la s h 370 fam ily, the C Y 7 C 3 73 is designed to bring the ease of use and high p e rfo rm an ce of th e 2 2 V 10 to h ig h -d e n s ity

Contextual Info: fax id: 6138 Y7C373Ì UltraLogic 64-Macrocell Flash CPLD • Pin compatible with the CY7C374i Features • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram mable ISR™ Flash technology

Contextual Info: fax id: 6138 Y7C373Î ^CYPRESS UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram mable ISR™ Flash technology

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Contextual Info: ¿? CYPRESS Y7C373 UltraLogic 64-Macrocell Flash CPLD Features Functional D escription • 6 4 m acrocells in fou r logic blocks • 6 4 I/O pins • 6 d ed icated in p u ts in clu d in g 4 clock p in s • N o h id d en delays T h e C Y 7 C 3 7 3 is a F lash e ra s a b le C o m p lex

Contextual Info: CY7C374Ì AD VAN CED INFORMATION 'WCYPRESSUltraLogic Features • 128 m acrocells in eigh t logic b lock s • 6 4 I/O pins • 6 d ed icated in p u ts in clu d in g 4 clock p in s • In -S ystem R ep rogram m ab le 1SR *“ F lash tech n ology — JTAG in terface