Y37384 Search Results

Y37384 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY37384 Contextual Info: PRELIMINARY C Y37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns Product-term clocking • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os	OCR Scan	Y37384 384-Macrocell 208-pin 256-lead CY37384	PDF
CY37512 Contextual Info: UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os	OCR Scan	512-Macrocell 208-pin 256/352-lead CY37512V, CY37512	PDF
CY37384 Abstract: tms 0119 256-pin Plastic BGA 17 x 17 Contextual Info: = m m m !Æ '^ r ^ r : c Q P R £ U M lm fíY Y37384 i í.-.-.-.í k v / k., UltraLogic 384-Macrocell ISR™ CPLD Features — ts = 5.5 ns — tc o = 6 ns • 384 m a cro c ells in 24 logic blo cks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™	OCR Scan	CY37384 384-Macrocell 208-pin 256-lead CY37384 tms 0119 256-pin Plastic BGA 17 x 17	PDF
y373 Abstract: CY37384 Contextual Info: ^ ^ ^ PRELIMINARY CYPRKSS Y37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — t co = 6.0 ns • 384 m a cro c ells in 24 logic blocks • P ro d uct-term clo ckin g • In-S ystem R e p ro g ra m m ab le ™ IS R ™ • IE E E 1149.1 JTAG b o u n d a ry scan	OCR Scan	CY37384 384-Macrocell y373 CY37384	PDF
O10S Contextual Info: PRELIMINARY Y37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD — t PD = 15 ns Features — ts = 8 ns • 384 macnocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes	OCR Scan	CY37384V 384-Macrocell O10S	PDF
CY37256P160-125UMB Abstract: CY37256P160-125AI CY37256P160-83UMB CY37256 CERAMIC QUAD FLATPACK CQFP CY37256V Contextual Info: CY37256 UltraLogic 256-Macrocell ISR™ CPLD — tc o = 4.5 ns Features P ro d uct-term clocking • 256 m a cro c ells in sixteen logic blocks IEEE 1149.1 JTAG b o u n d a ry scan • In-S ystem R ep ro g ra m m ab le ™ IS R ™ P ro g ram m a b le slew rate co n tro l on ind ividu al l/O s	OCR Scan	CY37256 256-Macrocell 154MHz 160-pin 208-pin CY37256P160-125UMB CY37256P160-125AI CY37256P160-83UMB CY37256 CERAMIC QUAD FLATPACK CQFP CY37256V	PDF
R/37512/37512V Contextual Info: W ARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — t PD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — ts = 8 ns — tco = 8 ns • Product-term clocking — JTAG-compliant on-board programming	OCR Scan	CY37512V 512-Macrocell R/37512/37512V	PDF