XXXJX Search Results

MTA02

Abstract: i860Xp MT 8222 Intel 82495 Cache Controller 3ce-14 LR1 D09 ahy 103 i860 64-Bit Microprocessor Performance Brief MCache Second Level Cache-Controller
Contextual Info: in t e ! 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM Two-Way, Set Associative, Secondary Cache for i860 XP Microprocessor 50 MHz “No Glue” Interface with CPU Configurable — Cache Size 256 or 512 Kbytes — Line Width 32, 64 or 128 Bytes — Memory Bus Width 64 or 128 Bits

cq603

Abstract: CQ60 2N70D2 cs40 cs3g U43D 2X S0T-23 R62G cj6s TE02
Contextual Info: Ì111111M. . PAGE 2 ; CPU-1 ÎS P G A PAGE 3 CPU-2 PAGE 4 O PTI PAGE 5 PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE 6 7 a 9 10 li 12 13 O P T I Ô 2C55T 3 2 K X 3 2 SRAM O P T I Ô 2C 55 6 , G P 10 PORT O P T I Ô 2 C 6 0 2 A ,• HDD , CDROM CONN.

40282

Contextual Info: REV OESCRPTION REVO BY DATE A RLSO ECRS20146 RCRASTA 0DUN92 03 0 *o^ B ECR S 40M9 RCRASTA 07APR94 .012 *.002 C ECR S 40282 RCRASTA PRODUCT NO 91731-001 60# 18N0V9* /] \L_± I VEW A VIEW *A* 18,80 .740 8,43 .332 J _ E d ^ ^ D fe m 2,00 .079 234 .100

HDAS-8MC

Contextual Info: 9 D A T E H D A S -1 6 , H D A S -8 L 12-Bit, 50kHz, Complete Data Acquisition Systems INNOVATION and EXCELLENCE FEATURES • • • • • • • • Miniature 62-pin cermanic package 12-Bit resolution, 50kHz throughput Full-scale input range from 50mV to 10V

Contextual Info: HIGH-SPEED 3.3V 64K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9089S/L Integrateci Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location • High-speed clock to data access

MX808

Abstract: DAS-16 HDAS-16 mx1606 MX-808
Contextual Info: 9 D A T E H D A S -1 6 , H D A S -8 12-Bit, 50kHz, Complete Data Acquisition Systems L INNOVATION and EXCELLENCE FEATURES • • • • • • • • Miniature 62-pin cermanic package 12-Bit resolution, 50kHz throughput Full-scale input range from 50mV to 10V

xxxjx

Contextual Info: in t e i 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM Two-Way, Set Associative, Secondary Cache for i860 xp Microprocessor 50 MHz “No Glue” Interface with CPU Configurable — Cache Size 256 or 512 Kbytes — Line Width 32, 64 or 128 Bytes — Memory Bus Width 64 or 128 Bits

S1998

Abstract: TFK 614
Contextual Info: HIGH-SPEED 32K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709079S/L FEATURES: • True Dual-Ported memory cells which allow simultaneous access of the same memory location • High-speed clock to data access — Commercial: 9/12/15ns max.

AH11-00093A

Abstract: 48F010-20F 48F010-25F 48F010-30F 48F010K-25F
Contextual Info: Philips Components-Signetics 48F010 Document No. ECN No. Date of Issue A u g ust 1990 Status P re lim ina ry S pecification 1024K-bit FLASH memory 128K x 8 M em ory P roducts DESCRIPTION FEATURES The 4 8 F 0 1 0 is a 10 24 K bit C M O S FLASH M em ory o rg a n ize d as 128K x 8