1000BASE-X
Abstract: vhdl code for defer block coding in mac transmitter verilog code for mdio protocol verilog code for MII phy interface DS200 xip2150 xilinx tcp vhdl
Contextual Info: zozo 1-Gigabit Ethernet MAC Core with PCS/PMA Sublayers 1000BASE-X or GMII v3.0 R DS200 (v1.1) April 30, 2003 Product Specification Features • LogiCORE Facts Single-speed 1-gigabit-per-second Ethernet Media Access Controller (MAC) Core Specifics •
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1000base-xds200vhdl code for defer block coding in mac transmitterverilog code for mdio protocol+3verilog code for mii phy interfacexip2150xilinx tcp vhdl
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DS201
Abstract: 10Gigabit Ethernet PHY vhdl code for ethernet mac spartan 3 VIRTEX-5 DDR PHY xilinx logicore fifo generator 6.2 vhdl code for ethernet csma cd MAC layer sequence number vhdl code for mac transmitter Xilinx ISE Design Suite 9.2i xilinx fifo 9.3
Contextual Info: 10-Gigabit Ethernet MAC v9.3 DS201 September 16, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gbps Ethernet Media Access Controller MAC solution enabling the design
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10-gigabitds20110gigabit ethernet phyvhdl code for ethernet mac spartan 3+7virtex-5 ddr phyxilinx logicore fifo generator 6.2vhdl code for ethernet csma cdmac layer sequence numbervhdl code for mac transmitterxilinx ise design suite 9.2ixilinx fifo 9.3
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GR-253
Abstract: XIP211 XIP2198 STS-192 vhdl code for frame synchronization Paxonet Communications
Contextual Info: CoreEl STS192c/STM64 Path Processor CC324 May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com
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sts192c/stm64cc324gr-253xip211+4xip2198sts-192vhdl code for frame synchronizationpaxonet communications
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vhdl code for spi
Abstract: vhdl code for spi xilinx OC192 OC48 XAPP525 verilog code for spi4.2 to fifo spi 4.2 master code verilog code for 16 bit ram SPI Verilog HDL vhdl code for DCM
Contextual Info: Application Note: Virtex-II Series R SPI-4.2 to Quad SPI-3 Bridge XAPP525 v2.0 October 15, 2004 Summary This application note describes a reference design used to bridge one 4-channel Xilinx SPI-4.2 (PL4) core (v6.1) to four 1-channel SPI-3 (PL3) Link Layer cores (v3.2). The design is
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xapp525oc192com/pub/applications/xapp/xapp525vhdl code for spi+7vhdl code for spi xilinxoc48verilog code for spi4.2 to fifospi 4.2 master codeverilog code for 16 bit ramspi verilog hdlvhdl code for dcm
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vhdl code for ethernet mac spartan 3
Abstract: xilinx fifo 9.3 Xilinx ISE Design Suite 9.2i crc verilog code 16 bit MAC layer sequence number vhdl code for mac transmitter 10Gigabit Ethernet PHY DS201
Contextual Info: LogiCORE IP 10-Gigabit Ethernet MAC v10.1 DS201 October 19, 2011 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gbps Ethernet Media Access Controller MAC solution enabling the design
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10-gigabitds201vhdl code for ethernet mac spartan 3xilinx fifo 9.3+5xilinx ise design suite 9.2icrc verilog code 16 bitmac layer sequence numbervhdl code for mac transmitter10gigabit ethernet phy
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P802
Abstract: XIP2092 XIP2093 XIP2094 XIP2095 XIP2096 XIP2097 10GBASE-SR DS201
Contextual Info: 10-Gigabit Ethernet MAC with XGMII or XAUI v2.1 DS201 v2.1 June 24, 2002 Product Specification LogiCORE Facts Core Specifics Features Supported Families Virtex-II, Virtex-II Pro Speed Grades Designed to Draft D4.1 of IEEE P802.3ae specification -5 speed grade on Virtex-II
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10-gigabitds20125mhz64-bit+8p802xip2092xip2093xip2094xip2095xip2096xip209710gbase-sr
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vhdl code for ethernet csma cd
Abstract: vhdl code for mac transmitter Ethernet-MAC VIRTEX-5 DDR PHY xilinx logicore fifo generator 6.2 MAC layer sequence number 10Gigabit Ethernet PHY Xilinx ISE Design Suite 9.2i DS201 vhdl code for ethernet mac spartan 3
Contextual Info: 10-Gigabit Ethernet MAC v9.2 DS201 June 24, 2009 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gbps Ethernet Media Access Controller MAC solution enabling the design
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10-gigabitds201vhdl code for ethernet csma cdvhdl code for mac transmitter+7ethernet-macvirtex-5 ddr phyxilinx logicore fifo generator 6.2mac layer sequence number10gigabit ethernet phyxilinx ise design suite 9.2ivhdl code for ethernet mac spartan 3
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10GBASE-LR
Abstract: 8B10B XIP2092 XIP2116 10Gigabit Ethernet PHY MDIO clause 45 specification 10GBASE-X DS201
Contextual Info: 10-Gigabit Ethernet MAC with XGMII or XAUI v3.0 DS201 v3.0 April 30, 2003 Product Specification Features • LogiCORE Facts Single-speed full-duplex 10-gigabits-per-second Ethernet Media Access Controller Supported Families Virtex-II, Virtex-II Pro •
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10-gigabitds20110-gigabits-per-second3ae-2002+710gbase-lr8b10bxip2092xip211610gigabit ethernet phymdio clause 45 specification10gbase-x
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